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Hardware Reference Manual 5
Contents
3.2.7 Power Management...............................................................................................81
3.2.8 Debugging .............................................................................................................81
3.2.9 JTAG......................................................................................................................81
3.3 Memory Management.........................................................................................................82
3.3.1 Architecture Model.................................................................................................82
3.3.1.1 Version 4 versus Version 5 ....................................................................82
3.3.1.2 Memory Attributes..................................................................................82
3.3.1.2.1 Page (P) Attribute Bit .............................................................82
3.3.1.2.2 Instruction Cache ...................................................................83
3.3.1.2.3 Data Cache and Write Buffer .................................................83
3.3.1.2.4 Details on Data Cache and Write Buffer Behavior.................83
3.3.1.2.5 Memory Operation Ordering ..................................................84
3.3.2 Exceptions .............................................................................................................84
3.3.3 Interaction of the MMU, Instruction Cache, and Data Cache.................................85
3.3.4 Control ...................................................................................................................85
3.3.4.1 Invalidate (Flush) Operation...................................................................85
3.3.4.2 Enabling/Disabling .................................................................................85
3.3.4.3 Locking Entries ......................................................................................86
3.3.4.4 Round-Robin Replacement Algorithm ...................................................87
3.4 Instruction Cache................................................................................................................88
3.4.1 Instruction Cache Operation ..................................................................................89
3.4.1.1 Operation when Instruction Cache is Enabled.......................................89
3.4.1.2 Operation when Instruction Cache is Disabled ......................................90
3.4.1.3 Fetch Policy ...........................................................................................90
3.4.1.4 Round-Robin Replacement Algorithm ...................................................90
3.4.1.5 Parity Protection.....................................................................................91
3.4.1.6 Instruction Cache Coherency.................................................................91
3.4.2 Instruction Cache Control ......................................................................................92
3.4.2.1 Instruction Cache State at Reset ...........................................................92
3.4.2.2 Enabling/Disabling .................................................................................92
3.4.2.3 Invalidating the Instruction Cache..........................................................92
3.4.2.4 Locking Instructions in the Instruction Cache ........................................92
3.4.2.5 Unlocking Instructions in the Instruction Cache .....................................94
3.5 Branch Target Buffer (BTB) ................................................................................................94
3.5.1 Branch Target Buffer Operation.............................................................................94
3.5.1.1 Reset......................................................................................................95
3.5.2 Update Policy.........................................................................................................96
3.5.3 BTB Control ...........................................................................................................96
3.5.3.1 Disabling/Enabling .................................................................................96
3.5.3.2 Invalidation.............................................................................................96
3.6 Data Cache.........................................................................................................................96
3.6.1 Overviews ..............................................................................................................97
3.6.1.1 Data Cache Overview ............................................................................97
3.6.1.2 Mini-Data Cache Overview ....................................................................98
3.6.1.3 Write Buffer and Fill Buffer Overview.....................................................99
3.6.2 Data Cache and Mini-Data Cache Operation ........................................................99
3.6.2.1 Operation when Caching is Enabled......................................................99
3.6.2.2 Operation when Data Caching is Disabled ............................................99
3.6.2.3 Cache Policies .....................................................................................100
3.6.2.3.1 Cacheability .........................................................................100
3.6.2.3.2 Read Miss Policy .................................................................100
3.6.2.3.3 Write Miss Policy..................................................................101