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Hardware Reference Manual 349
Intel
®
IXP2800 Network Processor
PCI Unit
9.5.1.5 Target Write Access Receives Bad Parity PCI_PAR with the Data
1. If PCI_CMD_STAT[PERR_RESP] is not set, PCI Unit will ignore the parity error.
2. If PCI_CMD_STAT[PERR_RESP] is set:
a. core asserts PCI_PERR_L and sets PCI_CMD_STAT[PERR].
b. Slave Interface sets PCI_CONTROL[TGT_WR_PAR], which will interrupt the Intel
XScale
®
core if enabled.
c. Data is discarded.
9.5.1.6 SRAM Responds with a Memory Error on One or More Data Phases
on a Target Read
1. Slave Interface sets PCI_CONTROL[TGT_SRAM_ERR], which will interrupt the Intel
XScale
®
core if enabled.
2. Assert PCI Target Abort at or before the data in question is driven on PCI.
9.5.1.7 DRAM Responds with a Memory Error on One or More Data Phases
on a Target Read
1. Slave Interface sets PCI_CONTROL[TGT_DRAM_ERR], which will interrupt the Intel
XScale
®
core if enabled.
2. Slave Interface asserts PCI Target Abort at or before the data in question is driven on PCI.
9.5.2 As a PCI Initiator During a DMA Transfer
9.5.2.1 DMA Read from DRAM (Memory-to-PCI Transaction) Gets a
Memory Error
1. Set PCI_CONTROL[DMA_DRAM_ERR] which will interrupt the Intel XScale
®
core if
enabled.
2. Master Interface terminates transaction before bad data is transferred (okay to terminate
earlier).
3. Master Interface clears the Channel Enable bit in CHAN_X_CONTROL.
4. Master Interface sets DMA channel error bit in CHAN_X_CONTROL.
5. Master Interface does not reset the DMA CSRs; This leaves the descriptor pointer pointing to
the DMA descriptor of the failed transfer.
6. Master Interface resets the state machines and DMA buffers.