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74 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Technical Description
2.9.3.3 DMA Channel End Operation
1. Channel owned by PCI:
If not masked via the PCI Outbound Interrupt Mask register, the DMA channel interrupts the
PCI host after the setting of the DMA done bit in the CHAN_X_CONTROL register, which is
readable in the PCI Outbound Interrupt Status register.
2. Channel owned by the Intel XScale
®
core:
If enabled via the Intel XScale
®
core Interrupt Enable registers, the DMA channel interrupts
the Intel XScale
®
core by setting the DMA channel done bit in the CHAN_X_CONTROL
register, which is readable in the Intel XScale
®
core Interrupt Status register.
3. Channel owned by Microengine:
If enabled via the Microengine Auto-Push Enable registers, the DMA channel signals the
Microengine after setting the DMA channel done bit in the CHAN_X_CONTROL register,
which is readable in the Microengine Auto-Push Status register.
2.9.3.4 Adding Descriptors to an Unterminated Chain
It is possible to add a descriptor to a chain while a channel is running. To do so, the chain should be
left unterminated, i.e., the last descriptor should have End of Chain clear, and the Chain Pointer
value equal to 0. A new descriptor (or linked list of descriptors) can be added to the chain by
overwriting the Chain Pointer value of the unterminated descriptor (in SRAM) with the Local
Memory address of the (first) added descriptor (the added descriptor must actually be valid in
Local Memory prior to that). After updating the Chain Pointer field, the software must write a 1 to
the Descriptor Added bit of the Channel Control register. This is necessary for the case where the
channel was paused to reactivate the channel. However, software need not check the state of the
channel before writing that bit; there is no side-effect of writing that bit in the case where the
channel had not yet read the unlinked descriptor.
If the channel was paused or had read an unlinked Pointer, it will re-read the last descriptor
processed (i.e., the one that originally had the 0 value for Chain Pointer) to get the address of the
newly added descriptor.
A descriptor cannot be added to a descriptor that has End of Chain set.
2.9.4 Mailbox and Message Registers
Mailbox and Doorbell registers provide hardware support for communication between the Intel
XScale
®
core and a device on the PCI Bus.
Four 32-bit mailbox registers are provided so that messages can be passed between the Intel
XScale
®
core and a PCI device. All four registers can be read and written with byte resolution from
both the Intel XScale
®
core and PCI. How the registers are used is application dependent and the
messages are not used internally by the PCI Unit in any way. The mailbox registers are often used
with the Doorbell interrupts.
Doorbell interrupts provide an efficient method of generating an interrupt as well as encoding the
purpose of the interrupt. The PCI Unit supports a 32-bit the Intel XScale
®
core DOORBELL
register that is used by a PCI device to generate an the Intel XScale
®
core interrupt, and a separate
32-bit PCI DOORBELL register that is used by the Intel XScale
®
core to generate a PCI interrupt.
A source generating the Doorbell interrupt can write a software defined bitmap to the register to
indicate a specific purpose. This bitmap is translated into a single interrupt signal to the destination