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Hardware Reference Manual 11
Contents
8.7.2.3 Single IXP2800 Network Processor.....................................................289
8.8 Interface to Command and Push and Pull Buses .............................................................290
8.8.1 RBUF or MSF CSR to Microengine S_TRANSFER_IN Register for Instruction:.291
8.8.2 Microengine S_TRANSFER_OUT Register to TBUF or
MSF CSR for Instruction:.....................................................................................291
8.8.3 Microengine to MSF CSR for Instruction: ............................................................291
8.8.4 From RBUF to DRAM for Instruction: ..................................................................291
8.8.5 From DRAM to TBUF for Instruction:...................................................................292
8.9 Receiver and Transmitter Interoperation with Framers and Switch Fabrics .....................292
8.9.1 Receiver and Transmitter Configurations ............................................................293
8.9.1.1 Simplex Configuration..........................................................................293
8.9.1.2 Hybrid Simplex Configuration ..............................................................294
8.9.1.3 Dual Network Processor Full Duplex Configuration.............................295
8.9.1.4 Single Network Processor Full Duplex Configuration (SPI-4.2)...........296
8.9.1.5 Single Network Processor, Full Duplex Configuration
(SPI-4.2 and CSIX-L1) .........................................................................297
8.9.2 System Configurations.........................................................................................297
8.9.2.1 Framer, Single Network Processor Ingress and Egress, and
Fabric Interface Chip............................................................................298
8.9.2.2 Framer, Dual Network Processor Ingress, Single
Network Processor Egress, and Fabric Interface Chip ........................298
8.9.2.3 Framer, Single Network Processor Ingress and Egress, and
CSIX-L1 Chips for Translation and Fabric Interface ............................299
8.9.2.4 CPU Complex, Network Processor, and Fabric Interface Chip ...........299
8.9.2.5 Framer, Single Network Processor, Co-Processor, and
Fabric Interface Chip............................................................................300
8.9.3 SPI-4.2 Support ...................................................................................................301
8.9.3.1 SPI-4.2 Receiver..................................................................................301
8.9.3.2 SPI-4.2 Transmitter..............................................................................302
8.9.4 CSIX-L1 Protocol Support ...................................................................................303
8.9.4.1 CSIX-L1 Interface Reference Model: Traffic Manager and Fabric
Interface Chip.......................................................................................303
8.9.4.2 Intel® IXP2800 Support of the CSIX-L1 Protocol ................................304
8.9.4.2.1 Mapping to 16-Bit Wide DDR LVDS ....................................304
8.9.4.2.2 Support for Dual Chip, Full-Duplex Operation .....................305
8.9.4.2.3 Support for Simplex Operation.............................................306
8.9.4.2.4 Support for Hybrid Simplex Operation .................................307
8.9.4.2.5 Support for Dynamic De-Skew Training...............................308
8.9.4.3 CSIX-L1 Protocol Receiver Support ....................................................309
8.9.4.4 CSIX-L1 Protocol Transmitter Support ................................................310
8.9.4.5 Implementation of a Bridge Chip to CSIX-L1 .......................................311
8.9.5 Dual Protocol (SPI and CSIX-L1) Support...........................................................312
8.9.5.1 Dual Protocol Receiver Support...........................................................312
8.9.5.2 Dual Protocol Transmitter Support.......................................................312
8.9.5.3 Implementation of a Bridge Chip to CSIX-L1 and SPI-4.2 ...................313
8.9.6 Transmit State Machine.......................................................................................314
8.9.6.1 SPI-4.2 Transmitter State Machine......................................................314
8.9.6.2 Training Transmitter State Machine.....................................................315
8.9.6.3 CSIX-L1 Transmitter State Machine ....................................................315
8.9.7 Dynamic De-Skew ...............................................................................................316
8.9.8 Summary of Receiver and Transmitter Signals ...................................................317