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200 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
DRAM
5.10.3 DRAM Read
When a read (or TBUF_WR, which does a DRAM read) command is at the head of the Command
Inlet FIFO, it is moved to the proper Bank CMD FIFO if there is room. If there is not enough room
in the Bank’s CMD FIFO, the read command waits at the head of the Command Inlet FIFO.
When a read command is at the head of the Bank CMD FIFO, and there is room for the read data in
the Push Data FIFO (including all reads in flight at the RDRAM), it will arbitrate for RMC. When
it wins arbitration, it sends the address and command to RMC. The Push_ID is put into the RP
FIFO (Read in Progress) to coordinate it with read data from RMC.
When read data is returned from RMC, it is placed into the Push_Data FIFO. Each Push_Data is
sent to the Push Arbiter with a Push_ID; the RDRAM controller increments the Push_ID for each
data phase. If Push Arbiter asserts the full signal, Push Data is stopped and held in the Push Data
skid FIFO. The Push Data is sent to the read destination under control of the Push Arbiter.
The destination of the Push Data can be either Intel XScale
®
core, PCI, TBUF, or Microengine, and
is specified in the Push_ID. When the destination is TBUF or PCI, data is taken at 64 bits per cycle.
When the destination is the Microengine or the Intel XScale
®
core, data is taken at 32 bits per
cycle. The Push Arbiter justifies the data to the low 32 bits of Push Data. The Microengine is
signaled when the last data is pushed.
5.10.4 CSR Write
When a CSR write command is at the head of the Command Inlet FIFO, it is moved to the CSR
CMD register, and the Pull_ID is sent to the Pull arbiter. This can only be done if the CSR CMD
register is not currently occupied. If it is, the CSR write command waits at the head of the
Command Inlet FIFO.
When the Pull_ID is sent to the Pull Arbiter, a tag is put into the PP FIFO (Pull in Progress); this
allows the channel to identify the Pull Data as CSR data when it arrives. When the CSR pull data
arrives, it is put into the addressed CSR, and the CSR CMD register is marked as empty.
5.10.5 CSR Read
When a CSR read command is at the head of the Command Inlet FIFO, it is moved to the CSR
CMD register. This can only be done if the CSR CMD register is not currently occupied. If it is, the
CSR read command waits at the head of the Command Inlet FIFO.
On the first available cycle in which RDRAM data from RMC is not being put into the Push Data
FIFO, the CSR data will be put into the Push Data FIFO. If it is convenient to guarantee a slot by
putting a bubble on the RMC input, then that will be done.