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398 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Performance Monitor Unit
45 Detect FC_DEAD MRX_CLK level separate
Indicates that a dead cycle has been
received on the RXCDAT inputs for greater
than 2 clock cycles; the valid signal from the
MTS_CLK domain is synchronized; as such,
it yields an approximate value.
46 Detect C_IDLE MR_CLK level separate
Indicates that an idle cycle has been
received on the RDAT inputs for greater
than 2 clock cycles; the valid signal from the
MTS_CLK domain is synchronized; as such,
it yields an approximate value.
47 Detect C_DEAD MR_CLK level separate
Indicates that a dead cycle has been
received on the RDAT inputs for greater
than 2 clock cycles; the valid signal from the
MTS_CLK domain is synchronized; as such,
it yields an approximate value.
48 Detect CFC sustained MTX_CLK level separate
Indicates that the CFC input flag has been
asserted for greater than 32 clock cycles;
the valid signal from the MTX_CLK domain
is synchronized; as such, it yields an
approximate value.
49 Rbuffer Partition 0 empty P_CLK level separate
Indicates that partition 0 of the rbuffer is
empty.
50 Rbuffer Partition 1 empty P_CLK level separate
Indicates that partition 1 of the rbuffer is
empty.
51 Rbuffer Partition 2 empty P_CLK level separate
Indicates that partition 2of the rbuffer is
empty.
52 Full Element List enqueue P_CLK pulse separate
53 Full Element List dequeue P_CLK pulse separate
54 Full Element List full P_CLK level separate
55 Full Element List not empty P_CLK level separate
56 Rbuffer Partition 0 full P_CLK level separate Indicates that partition 0 of the rbuffer is full.
57 Rbuffer Partition 1 full P_CLK level separate Indicates that partition 1 of the rbuffer is full.
58 Rbuffer Partition 2 full P_CLK level separate Indicates that partition 2of the rbuffer is full.
59 reserved
60 Rx_Valid[0] is set P_CLK separate
61 Rx_Valid[8] is set P_CLK separate
62 Rx_Valid[16] is set P_CLK separate
63 Rx_Valid[24] is set P_CLK separate
64 Rx_Valid[32] is set P_CLK separate
65 Rx_Valid[48] is set P_CLK separate
66 Rx_Valid[64] is set P_CLK separate
67 Rx_Valid[96] is set P_CLK separate
68 Data CFrame received P_CLK pulse separate
Indicates that the CSIX DATA state machine
after the Receive input FIFO has received a
CSIX DATA CFRAME.
69 Control CFrame received P_CLK pulse separate
Indicates that the CSIX CONTROL state
machine after the Receive input FIFO has
received a CSIX CONTROL CFRAME.
Table 157. IXP2800 Network Processor MSF PMU Event List (Sheet 3 of 6)