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Hardware Reference Manual 371
Intel
®
IXP2800 Network Processor
Clocks and Reset
Figure 135. Boot Process
A9782-03
No Yes
Reset Signal asserted
(hardware, software, PCI or Watchdog)
CFG_PROM_BOOT-
Boot From Present
START
Yes No
CFG_PROM_
BOOT_HOST
STARTSTARTSTARTSTART
1. Intel XScale
®
Core is
held in reset.
2. PCI BAR window sizes
are configured by strap
options.
3. External PCI host
configures PCI registers
and DRAM registers.
4. External PCI host loads
boot image in DRAM.
5. Release Intel XScale
®
Core from reset and Intel
XScale
®
Core starts code
fetch from DRAM at 0x0.
Intel XScale
®
Core
initializes the system
by initiating PCI
config cycles.
1. Intel XScale
®
Core boots
off PROM.
2. Configures SRAM, DRAM,
Media, etc.
3. If CFG_RST# signal after
1 ms timeout once PCI
clock active is detected.
4. Retries PCI config cycles.
5. Programs PCI BAR
window size.
6. Intel XScale
®
Core writes
the IXP_RESET0[21]
register to enable PCI bus.
Reset Signal deasserted. If CFG_RST_DIR
is 1, the Network Processor drives PCI
RST# signal. If CFG_RST_DIR is 0,
PCI_RST# is input.
END