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Hardware Reference Manual 167
Intel
®
IXP2800 Network Processor
Microengines
Microengines 4
This section defines the Network Processor Microengine (ME). This is the second version of the
Microengine, and is often referred to as the MEv2 (Microengine Version 2).
4.1 Overview
The following sections describe the programmer’s view of the Microengine. The block diagram in
Figure 56 is used in the description. Note that this block diagram is simplified for clarity, not all
interface signals are shown, and some blocks and connectivity have been omitted to make the
diagram more readable. This block diagram does not show any pipeline stages, rather it shows the
logical flow of information.
The Microengine provides support for software controlled multi-threaded operation. Given the
disparity in processor cycle times versus external memory times, a single thread of execution will
often block waiting for external memory operations to complete. Having multiple threads available
allows for threads to interleave operation—there is often at least one thread ready to run while
others are blocked.