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96 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Intel XScale
®
Core
3.5.2 Update Policy
A new entry is stored into the BTB when the following conditions are met:
• The branch instruction has executed
• The branch was taken
• The branch is not currently in the BTB
The entry is then marked valid and the history bits are set to WT. If another valid branch exists at
the same entry in the BTB, it will be evicted by the new branch.
Once a branch is stored in the BTB, the history bits are updated upon every execution of the branch
as shown in Figure 21.
3.5.3 BTB Control
3.5.3.1 Disabling/Enabling
The BTB is always disabled with Reset. Software can enable the BTB through a bit in a
coprocessor register.
Before enabling or disabling the BTB, software must invalidate it (described in the following
section). This action will ensure correct operation in case stale data is in the BTB. Software should
not place any branch instruction between the code that invalidates the BTB and the code that
enables/disables it.
3.5.3.2 Invalidation
There are four ways the contents of the BTB can be invalidated.
1. Reset.
2. Software can directly invalidate the BTB via a CP15, register 7 function.
3. The BTB is invalidated when the Process ID register is written.
4. The BTB is invalidated when the instruction cache is invalidated via CP15, register 7
functions.
3.6 Data Cache
The Intel XScale
®
core data cache enhances performance by reducing the number of data accesses
to and from external memory. There are two data cache structures in the Intel XScale
®
core, a 32-
Kbyte data cache and a 2-Kbyte mini-data cache. An eight entry write buffer and a four entry fill
buffer are also implemented to decouple the Intel XScale
®
core instruction execution from external
memory accesses, which increases overall system performance.