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Hardware Reference Manual 189
Intel
®
IXP2800 Network Processor
DRAM
5.3 DRAM Clocking
Figure 66 shows the clock generation for one channel (this description is just for reference; for
more information, refer to Rambus* design literature). The other channels use the same
configuration.
Note: Refer to Section 10 for additional information on clocking.
The RDRAM Controller receives two clocks, both generated internal to the IXP2800 Network
Processor.
The internal clock, is used to control all logic associated with communication with other on-chip
Units. This clock is ½ of the Microengine frequency, and is in the range of 500 – 700 MHz.
The other clock, the Rambus* Memory Controller (RMC) clock, is internally divided by two and
brought out on the CLK_PHASE_REF pin, which is then used as the reference clock for the DRCG
(see Figure 67 and Figure 68). The reason for this is that our internal RMC clock is derived from
the Microengine clock (supported programmable divide range is from 8 – 15 for the A stepping and
6 – 15 for the B stepping) at a Microengine frequency of 1.4 GHz (the available RMC clock
frequencies are 100 MHz and 127 MHz). In the RMC implementation, we have a fixed 1:1 clock
relationship between the RMC clock and the SYNCLK (SYNCLK = Clock-to-Master(CTM)/4); to
maintain this relationship, we provide the clock to the DRCG. The CTM is received by the DRAM
controller which it drives back out as Clock-from-Master (CFM). Additionally, the controller
creates PCLKM and SYNCLKN, which are also driven to the DRCG.
Figure 66. Clock Configuration
A9726-02
PCLKM
SYNCLKN
CTM, nCTM
CFM, nCFM
RDRAM RDRAM
CLK_PHASE_REF
Intel
®
IXP2800
Network
Processor
Direct
Rambus*
Clock
Generator
(DRCG)
REF_CLK