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16 Hardware Reference Manual
Contents
Figures
1 IXP2800 Network Processor Functional Block Diagram ............................................................ 28
2 IXP2800 Network Processor Detailed Diagram.......................................................................... 29
3 Intel XScale® Core 4-GB (32-Bit) Address Space ..................................................................... 32
4 Microengine Block Diagram........................................................................................................ 34
5 Context State Transition Diagram .............................................................................................. 36
6 Byte-Align Block Diagram........................................................................................................... 44
7 CAM Block Diagram ................................................................................................................... 46
8 Echo Clock Configuration ........................................................................................................... 52
9 Logical View of Rings ................................................................................................................. 57
10 Example System Block Diagram ................................................................................................ 59
11 Full-Duplex Block Diagram ......................................................................................................... 60
12 Simplified MSF Receive Section Block Diagram ........................................................................ 61
13 Simplified Transmit Section Block Diagram................................................................................ 65
14 Hash Unit Block Diagram ........................................................................................................... 70
15 DMA Descriptor Reads............................................................................................................... 72
16 Intel XScale
®
Core Architecture Features .................................................................................. 80
17 Example of Locked Entries in TLB ............................................................................................. 88
18 Instruction Cache Organization .................................................................................................. 89
19 Locked Line Effect on Round Robin Replacement..................................................................... 93
20 BTB Entry ................................................................................................................................... 95
21 Branch History ............................................................................................................................ 95
22 Data Cache Organization ........................................................................................................... 97
23 Mini-Data Cache Organization ...................................................................................................98
24 Byte Steering for Read and Byte-Enable Generation by the Intel XScale
®
Core ..................... 122
25 Intel XScale® Core-Initiated Write to the IXP2800 Network Processor.................................... 124
26 Intel XScale® Core-Initiated Write to the IXP2800 Network Processor (Continued)................ 125
27 Global Buses Connection to the Intel XScale® Core Gasket ................................................... 126
28 Flow Through the Intel XScale
®
Core Interrupt Controller........................................................ 132
29 Interrupt Mask Block Diagram ..................................................................................................133
30 XPI Interfaces for IXP2800 Network Processor........................................................................ 135
31 UART Data Frame.................................................................................................................... 138
32 GPIO Functional Diagram ........................................................................................................140
33 Timer Control Unit Interfacing Diagram .................................................................................... 141
34 Timer Internal Logic Diagram ...................................................................................................142
35 Slowport Unit Interface Diagram...............................................................................................144
36 Address Space Hole Diagram .................................................................................................. 145
37 Slowport Example Application Topology .................................................................................. 146
38 Mode 0 Single Write Transfer for a Fixed-Timed Device.......................................................... 147
39 Mode 0 Single Write Transfer for a Self-Timing Device ........................................................... 148
40 Mode 0 Single Read Transfer for Fixed-Timed Device ............................................................ 149
41 Mode 0 Single Read Transfer for a Self-Timing Device ........................................................... 150
42 An Interface Topology with Lucent* TDAT042G5 SONET/SDH............................................... 152
43 Mode 1 Single Write Transfer for Lucent* TDAT042G5 Device (B0) ....................................... 153
44 Mode 1 Single Read Transfer for Lucent* TDAT042G5 Device (B0) ....................................... 154
45 An Interface Topology with PMC-Sierra* PM5351 S/UNI-TETRA* .......................................... 155
46 Mode 2 Single Write Transfer for PMC-Sierra* PM5351 Device (B0) ...................................... 156
47 Mode 2 Single Read Transfer for PMC-Sierra* PM5351 Device (B0) ...................................... 157