Filter
Top Products
Hardware Reference Manual 209
Intel
®
IXP2800 Network Processor
SRAM Interface
In general, QDR and QDR II bursts of two SRAMs are supported at speeds up to 233 MHz. As
other (larger) QDR SRAMs are introduced, they will also be supported.
The SRAM controller can also be configured to interface to an external coprocessor that adheres to
the QDR or QDR II electrical and functional specification.
6.2.1 Internal Interface
Each SRAM channel receives commands through the command bus mechanism and transfers data
to and from the Microengines, the Intel XScale
®
core, and PCI, using SRAM push and SRAM pull
buses.
6.2.2 Number of Channels
The IXP2800 Network Processor supports four channels.
6.2.3 Coprocessor and/or SRAMs Attached to a Channel
Each channel supports the attachment of QDR SRAMs, a co-processor, or both, depending on the
module level signal integrity and loading.
6.3 SRAM Controller Configurations
There are enough address pins (24) to support up to 64 Mbytes of SRAM. The SRAM controllers
can directly generate multiple port enables (up to five pairs) to allow for depth expansion. Two
pairs of pins are dedicated for port enables. Smaller RAMs use fewer address signals than the
number provided to accommodate the largest RAMs, so some address pins (23:18) are
configurable as either address or port-enable based on CSR SRAM_Control[Port_Control] as
shown in Table 70.
Note: All of the SRAMs on a given channel must be the same size.
Note: Table 70 shows the capability of the logic — 1, 2, or 4 loads are supported as shown in the table,
but this is subject to change.
Table 70. SRAM Controller Configurations
SRAM
Configuration
SRAM Size
Addresses Needed
to Index SRAM
Addresses Used
as Port Enables
Total Number of Port
Select Pairs Available
512K x 18 1 Mbyte 17:0 23:22, 21:20 4
1M x 18 2 Mbytes 18:0 23:22, 21:20 4
2M x 18 4 Mbytes 19:0 23:22, 21:20 4
4M x 18 8 Mbytes 20:0 23:22 3
8M x 18 16 Mbytes 21:0 23:22 3
16M x 18 32 Mbytes 22:0 None 2
32M x 18 64 Mbytes 23:0 None 1