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Hardware Reference Manual 377
Intel
®
IXP2800 Network Processor
Performance Monitor Unit
11.1.3 Functional Overview of CHAP Counters
At the heart of the CHAP counter’s functionality are counters, each with associated registers. Each
counter has a corresponding command, event, status, and data register. The smallest
implementation has two counters, but if justified for a particular product, this architecture can
support many more counters. The primary consideration is available silicon area. The memory-
mapped space currently defined can accommodate registers for 256 counters. It can be configured
for more, but that is beyond what is currently practical.
Signals that represent events from throughout the chip are routed to the CHAP unit. Software can
select events that are recorded during a measurement session. The number of counters in an
implementation defines the number of events that can be recorded simultaneously. Software and
hardware events can control the starting, stopping, and sampling of the counters. This can be done
in a time-based (polling) or an event-based fashion. Each counter can be incremented or
decremented by different events. In addition to simple counting of events, the unit can provide data
for histograms, queue analysis, and conditional event counting (for example, the number of times
that event A happens before the first event B takes place).
When a counter is sampled, the current value of the counter is latched into the corresponding data
register. The command, event, status, and data registers are accessible via standard Advanced
Peripheral Bus (APB) memory-mapped registers, to facilitate high-speed sampling.
Two optional external pins allow for external visibility and control of the counters. The output pin
signals that one of the following conditions generated an interrupt from any one of the counters:
• A programmable threshold condition was true.
• A command was triggered to begin.
• A counter overflow or underflow occurred.
The input pin allows an external source to control when a CHAP command is executed.
Figure 137 represents a single counter block. The multiplexers, registers, and all other logic are
repeated for each counter that is present. There is a threshold event from each counter block that
feeds into each multiplexer.