Filter
Top Products
Hardware Reference Manual 253
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
8.2.2.2 CSIX
CSIX CFrames are placed into either RBUF or FCEFIFO as follows:
At chip reset, all RBUF elements are marked invalid (available) and FCEFIFO is empty.
When a Base Header is sent (i.e., when RxSof is asserted) it is placed in a temporary holding
register. The Ready Field is extracted and held to be put into FC_Egress_Status CSR when (and
if) the entire CFrame is received without error. The Type field is extracted and used to index into
CSIX_Type_Map CSR to determine one of four actions.
• Discard (except for the Ready Field as described in Section 8.2.7.2.1).
• Place into RBUF Control CFrame partition.
• Place into RBUF Data CFrame partition.
• Place into FCEFIFO.
Note: Normally Idle CFrames (Type 0x0) will be discarded, Command and Status CFrames (Type 0x7)
will be placed into Control Partition, Flow Control CFrames (Type 0x6) will be placed into
FCEFIFO, and all others will be placed into Data Partition (see Table 87). The remapping done
through the CSIX_Type_Map CSR allows for more flexibility in usage, if desired.
If the action is Discard, the CFrame is discarded (except for the Ready Field as described in
Section 8.2.7.2.1). The Base Header, as well as Extension Header and Payload (if any) are
discarded.
If the destination is FCEFIFO:
The Payload is placed into the FCEFIFO, to be sent to the Ingress IXP2800 Network Processor
over the TXCDAT pins. If there is not enough room in FCEFIFO for the entire CFrame, based on
the Payload Size in the Base Header, the entire CFrame is discarded and
MSF_Interrupt_Status[FCEFIFO_Overflow] is set.
If the destination is RBUF (either Control or Data):
An available RBUF element of the corresponding type is allocated by receive control logic. If there
is not an available element, the CFrame is discarded and
MSF_Interrupt_Status[RBUF_Overflow] is set. Note that this normally should not happen
because, when the number of RBUF elements falls below a programmed limit, backpressure is sent
to the Switch Fabric. (Refer to Section 8.2.7.2.) The Type, Payload Length, CR (CSIX Reserved),
and P (Private) bits, and (subsequently arriving) Extension Header are placed into a temporary
status register. As the Payload (including padding if any) is received, it is placed into the allocated
RBUF element, starting at offset 0x0. (Note that it is more exact to state that the first four bytes
after the Base Header are placed into the status register as Extension Header. For Flow Control
CFrames, there is no Extension Header; the first four bytes are part of the Payload. They would be
found in the Extension Header field of the Status — no bytes are lost.)
When all of the Payload data (including padding if any), as indicated by the Payload Length field,
and Vertical Parity has been received, the element is marked valid. If another RxSof is received
prior to receiving the entire Payload, the element is also marked valid, and the Length Error status
bit is set. If the Payload Length field of the Base Header is greater than the element size (as
configured in MSF_Rx_Control[RBUF_Element_Size], then the Length Error bit in the status
will be set, and all payload bytes above the element size will be discarded. The temporary status
register value is put into Full_Element_List.