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340 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
PCI Unit
9.4 Master Interface Block
The Master Interface consists of the DMA engine and the Push/pull target interface. Both can
generate initiator PCI transactions.
9.4.1 DMA Interface
There are two DMA channels, each of which can move blocks of data from DRAM to the PCI or
from the PCI to DRAM. The DMA channels read parameters from a list of descriptors in SRAM,
perform the data movement to or from DRAM, and stop when the list is exhausted. The descriptors
are loaded from predefined SRAM entries or may be set directly by CSR writes to DMA registers.
There is no restriction on byte alignment of the source address or the destination address. For PCI
to DRAM transfers, the PCI command is Memory Read, Memory Read line, or Memory Read
Multiple. For DRAM to PCI transfers, the PCI command is Memory Write. Memory Write
Invalidate is not supported.
DMA reads are unmasked reads (all byte enables asserted) from DRAM. After each transfer, the
byte count is decremented by the number of bytes read, and the source address is incremental by
one 64-bit double Dword. The whole data block is fetched from the DRAM. For a system using
RDRAM (like the IXP2800 Network Processor), the block size is 16 bytes.
DMA reads are masked reads from the PCI and writes are masked for both the PCI and DRAM.
When moving a block of data, the internal hardware adjusts the byte enables so that the data is
aligned properly on block boundaries and that only the correct bytes are transferred if the initial
and final data requires masking.
For DMA data, the DMA FIFO consists of two separate FBus initiator read FIFOs and two initiator
write FIFOs, which are inside the PCI Core and three DMA buffers (corresponding to the DMA
channels), which buffer data to and from the DRAM. Since there is no simultaneous DMA read and
write outstanding, one shared 64-byte buffer is used for both read and write DRAM data
Up to two DMA channels are running at a time with three descriptors outstanding. The two DMA
channels and the direct access channel to PCI Bus from Command Bus Master are contending to
use the address, read and write FIFOs inside the Core.
Effectively, the active channels interleave bursts to or from the PCI Bus. Each channel is required
to arbitrate for the PCI FIFOs after each PCI burst request.