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Hardware Reference Manual 81
Intel
®
IXP2800 Network Processor
Intel XScale
®
Core
3.2.3 Instruction Cache
The Intel XScale
®
core implements a 32-Kbyte, 32-way set associative instruction cache with a
line size of 32 bytes. All requests that “miss” the instruction cache generate a 32-byte read request
to external memory. A mechanism to lock critical code within the cache is also provided.
3.2.4 Branch Target Buffer (BTB)
The Intel XScale
®
core provides a Branch Target Buffer to predict the outcome of branch type
instructions. It provides storage for the target address of branch type instructions and predicts the
next address to present to the instruction cache when the current instruction address is that of a
branch.
The BTB holds 128 entries.
3.2.5 Data Cache
The Intel XScale
®
core implements a 32-Kbyte, a 32-way set associative data cache and a 2-Kbyte,
2-way set associative mini-data cache. Each cache has a line size of 32 bytes, and supports write-
through or write-back caching.
The data/mini-data cache is controlled by page attributes defined in the MMU Architecture and by
coprocessor 15. The Intel XScale
®
core allows applications to reconfigure a portion of the data
cache as data RAM. Software may place special tables or frequently used variables in this RAM.
3.2.6 Performance Monitoring
Two performance monitoring counters have been added to the Intel XScale
®
core that can be
configured to monitor various events. These events allow a software developer to measure cache
efficiency, detect system bottlenecks, and reduce the overall latency of programs.
3.2.7 Power Management
The Intel XScale
®
core incorporates a power and clock management unit that can assist in
controlling clocking and managing power.
3.2.8 Debugging
The Intel XScale
®
core supports software debugging through two instruction address breakpoint
registers, one data-address breakpoint register, one data-address/mask breakpoint register, and a
trace buffer.
3.2.9 JTAG
Testability is supported on the Intel XScale
®
core through the Test Access Port (TAP) Controller
implementation, which is based on IEEE 1149.1 (JTAG) Standard Test Access Port and Boundary-
Scan Architecture. The purpose of the TAP controller is to support test logic internal and external
to the Intel XScale
®
core such as built-in self-test, boundary-scan, and scan.