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276 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
The information transmitted on TXCSRB can be read in FC_Egress_Status CSR, and the
information received on RXCSRB can be read in FC_Ingress_Status CSR.
The TXCSRB or RXCSRB signals carry the Ready information in a serial stream. Four bits of data
are carried in 10 clock phases, LSB first, as shown in Table 103.
The Transmit Data Ready bit sent from Egress to Ingress IXP2800 Network Processor will be
deasserted if the following condition is met.
• RBUF CSIX Data partition is full, based on HWM_Control[RBUF_D_HWM].
The Transmit Control Ready bit sent from the Egress to the Ingress IXP2800 Network Processor
will be deasserted if either of the following conditions is met.
• RBUF CSIX Control partition is full, based on HWM_Control[RBUF_C_HWM].
• FCEFIFO full, based on HWM_Control[FCEFIFO_HWM].
8.5.2 FCIFIFO and FCEFIFO Buffers
FCIFIFO and FCEFIFO are 1-Kbyte (256 entry x 32-bit) buffers for the flow control information.
FCEFIFO holds data while it is being transmitted off of the Egress IXP2800 Network Processor.
FCIFIFO holds data received into the Ingress IXP2800 Network Processor until Microengines can
read it. There are two usage models for the FIFOs — Full Duplex Mode and Simplex Mode,
selected by MSF_Rx_Control[Duplex_Mode].
Table 103. SRB Definition by Clock Phase Number
Clock
Cycle
Number
Description
Source of bit on Egress IXP2800 Network
Processor (TXCSRB)
Use of bit on Ingress IXP2800 Network
Processor (RXCSRB)
0–5
Framing information. Data is 000001; this pattern allows the Ingress IXP2800 Network Processor to
get synchronized to the serial stream regardless of the data values.
6
Most recently received Control Ready from a
CFrame Base Header.
Also visible in
FC_Egress_Status[SF_CReady].
When 0—Stop sending Control CFrames to the
Switch Fabric.
When 1—OK to send Control CFrames to the
Switch Fabric.
Also visible in FC_Ingress_Status[SF_CReady].
7
Most recently received Data Ready from a
CFrame Base Header.
Also visible in
FC_Egress_Status[SF_DReady]
When 0—Stop sending Data CFrames to the
Switch Fabric.
When 1—OK to send Data CFrames to the
Switch Fabric.
Also visible in FC_Ingress_Status[SF_DReady].
8
RBUF or FCEFIFO are above high water mark.
Also visible in
FC_Egress_Status[TM_CReady].
Place this bit in the Control Ready bit of all
outgoing CSIX Base Headers.
Also visible in
FC_Ingress_Status[TM_CReady].
9
RBUF is above high water mark.
Also visible in
FC_Egress_Status[TM_DReady].
Place this bit in the Data Ready bit of all outgoing
CSIX Base Headers.
Also visible in
FC_Ingress_Status[TM_DReady].