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Hardware Reference Manual 13
Contents
9.4.2 Push/Pull Command Bus Target Interface...........................................................345
9.4.2.1 Command Bus Master Access to Local Configuration Registers ........345
9.4.2.2 Command Bus Master Access to Local Control and
Status Registers...................................................................................346
9.4.2.3 Command Bus Master Direct Access to PCI Bus ................................346
9.4.2.3.1 PCI Address Generation for IO and MEM Cycles................346
9.4.2.3.2 PCI Address Generation for Configuration Cycles...............347
9.4.2.3.3 PCI Address Generation for Special and IACK Cycles........347
9.4.2.3.4 PCI Enables .........................................................................347
9.4.2.3.5 PCI Command .....................................................................347
9.5 PCI Unit Error Behavior ....................................................................................................348
9.5.1 PCI Target Error Behavior ...................................................................................348
9.5.1.1 Target Access Has an Address Parity Error ........................................348
9.5.1.2 Initiator Asserts PCI_PERR_L in Response to One of Our Data
Phases .................................................................................................348
9.5.1.3 Discard Timer Expires on a Target Read.............................................348
9.5.1.4 Target Access to the PCI_CSR_BAR Space Has Illegal
Byte Enables........................................................................................348
9.5.1.5 Target Write Access Receives Bad Parity PCI_PAR with the Data.....349
9.5.1.6 SRAM Responds with a Memory Error on One or More Data Phases
on a Target Read .................................................................................349
9.5.1.7 DRAM Responds with a Memory Error on One or More Data Phases
on a Target Read .................................................................................349
9.5.2 As a PCI Initiator During a DMA Transfer............................................................349
9.5.2.1 DMA Read from DRAM (Memory-to-PCI Transaction) Gets a
Memory Error .......................................................................................349
9.5.2.2 DMA Read from SRAM (Descriptor Read) Gets a Memory Error ........350
9.5.2.3 DMA from DRAM Transfer (Write to PCI) Receives PCI_PERR_L on
PCI Bus................................................................................................350
9.5.2.4 DMA To DRAM (Read from PCI) Has Bad Data Parity .......................350
9.5.2.5 DMA Transfer Experiences a Master Abort (Time-Out) on PCI ...........351
9.5.2.6 DMA Transfer Receives a Target Abort Response During a
Data Phase ..........................................................................................351
9.5.2.7 DMA Descriptor Has a 0x0 Word Count (Not an Error) .......................351
9.5.3 As a PCI Initiator During a Direct Access from the Intel
XScale® Core or Microengine .............................................................................351
9.5.3.1 Master Transfer Experiences a Master Abort (Time-Out) on PCI ........351
9.5.3.2 Master Transfer Receives a Target Abort Response During
a Data Phase .......................................................................................351
9.5.3.3 Master from the Intel XScale® Core or Microengine Transfer
(Write to PCI) Receives PCI_PERR_L on PCI Bus .............................352
9.5.3.4 Master Read from PCI (Read from PCI) Has Bad Data Parity ............352
9.5.3.5 Master Transfer Receives PCI_SERR_L from the PCI Bus ................352
9.5.3.6 Intel XScale® Core Microengine Requests Direct Transfer when
the PCI Bus is in Reset ........................................................................352
9.6 PCI Data Byte Lane Alignment .........................................................................................352
9.6.1 Endian for Byte Enable ........................................................................................355
10 Clocks and Reset.......................................................................................................................359
10.1 Clocks ...............................................................................................................................359
10.2 Synchronization Between Frequency Domains ................................................................363
10.3 Reset ................................................................................................................................364
10.3.1 Hardware Reset Using nRESET or PCI_RST_L .................................................364