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Hardware Reference Manual 341
Intel
®
IXP2800 Network Processor
PCI Unit
9.4.1.1 Allocation of the DMA Channels
Static allocation are employed such that the DMA resources are controlled exclusively by a single
device for each channel. The Intel XScale
®
core, a Microengine and the external PCI host can
access the two DMA channels. The first two channels can function in one of the following modes,
as determined by the DMA_INF_MODE register:
• The Intel XScale
®
core owns both DMA channel 1 and channel 2.
• The Microengines owns both DMA channel 1 and channel 2.
• PCI host owns both DMA channel 1 and channel 2.
• The Intel XScale
®
core owns both DMA channel 1 and channel 2.
The third channel can be allocated to either the Intel XScale
®
core, PCI host, or Microengines.
The DMA mode can be changed only by the Intel XScale
®
core under software control. The
software should signal to suspend DMA transactions and wait until all DMA channels are free
before changing the mode. Software should determine when all DMA channels are free either by
polling XSCALE_INT_STATUS register bits DMA1 and DMA3 until both DMA channels are
done.
9.4.1.2 Special Registers for Microengine Channels
Interrupts are generated at the end of DMA operation for the Intel XScale
®
core and PCI-initiated
DMA. However, the Microengine does not provide the interrupt mechanism. The PCI Unit will
instead use an “Auto-Push” mechanism to signal the particular Microengine on completion of
DMA.
When the Microengine sets up the DMA channel, it would also write the CHAN_X_ME_PARAM
with Microengine number, Context number, Register number, and Signal number. When the DMA
channel completes, it writes some status information (Error or OK status) to the Microengine/
Context/Register/Signal. PCI Unit will arbitrate for the SRAM Push bus. The Push ID is from the
parameters in the register.
The ME_PUSH_STATUS reflects the DMA Done bit in each of the CHAN_X_CONTROL
registers. The Auto-Push operation will proceed after the DMA is done for the particular DMA
channel if the corresponding enable bit in the ME_PUSH_ENABLE is set.