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Hardware Reference Manual 147
Intel
®
IXP2800 Network Processor
Intel XScale
®
Core
3.12.7.6.1 Mode 0 Single Write Transfer for Fixed-Timed Device
Figure 38, shows the single write transfer for a fixed-timed device with the CSR programmed to a
value of setup=4, pulse width=0, and hold=2, followed by another read transfer.
The transaction is initiated with SP_ALE_L asserted. It latches the address from the SP_AD[7:0]
bus into the external buffer, using three clock cycles. After that, it should deassert the SP_ALE_L
to disable latching the address into the buffers.
The SP_A[1:0] signals span the whole transaction cycle.
For the write, it drives the data onto the SP_AD[7:0]. Meanwhile, it asserts the SP_CS_L[1:0]
signals. Depending on the timing control setup parameter, for this case, the SP_WR_L is not
asserted until four clock cycles have elapsed. The SP_CS_L[1:0] signals are deasserted two clocks
after the SP_WR_L is deasserted.
Figure 38. Mode 0 Single Write Transfer for a Fixed-Timed Device
A9706-02
SP_CLK
SP_ALE_L
SP_CS_L
[1:0]
SP_WR_L
D[7:0]
A[1:0]
17:10 24:189:2 17:10 24:189:2
SP_RD_L
SP_A[1:0]
SP_AD[7:0]
20 4 6 8 10 12 14 16 18 20