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Hardware Reference Manual 411
Intel
®
IXP2800 Network Processor
Performance Monitor Unit
11.4.6.8 ME02 Events Target ID(100010) / Design Block #(1001)
11.4.6.9 ME03 Events Target ID(100011) / Design Block #(1001)
Table 162. ME02 PMU Event List
Event
Number
Event Name
Clock
Domain
Pulse/
Level
Burst Description
Note:
1. All the Microengines have the same event list.
2. CC_Enable bit[2:0] is PMU_CTX_Monitor in Microengine CSR, This field holds the number of context to be monitored. The
event count only reflects the events that occur when this context is executing.
CC_Enable[2:0] = 000, select context number 0,
CC_Enable[2:0] = 001, select context number 1,
.......
CC_Enable[2:0] = 111, select context number 7.
3. 1.4 GHz events are sampled by the PMU at a 700 MHz rate. For this reason, all 1.4 GHz events have both an even and an odd
event. To determine the total number of 1.4 GHz events, the occurrences of the even events and odd events should be added
together.
4. For IXP2800 Network Processor Rev B, CC_Enable[3] must be set to 1 on all 16 Microengines for proper PMU functionality.
Table 163. ME03 PMU Event List
Event
Number
Event Name
Clock
Domain
Pulse/
Level
Burst Description
Note:
1. All the Microengines have the same event list.
2. CC_Enable bit[2:0] is PMU_CTX_Monitor in Microengine CSR, This field holds the number of context to be monitored. The
event count only reflects the events that occur when this context is executing.
CC_Enable[2:0] = 000, select context number 0,
CC_Enable[2:0] = 001, select context number 1,
.......
CC_Enable[2:0] = 111, select context number 7.
3. 1.4 GHz events are sampled by the PMU at a 700 MHz rate. For this reason, all 1.4 GHz events have both an even and an odd
event. To determine the total number of 1.4 GHz events, the occurrences of the even events and odd events should be added
together.
4. For IXP2800 Network Processor Rev B, CC_Enable[3] must be set to 1 on all 16 Microengines for proper PMU functionality.