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362 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Clocks and Reset
Figure 131 shows the clocks generation circuitry for the IXP2800 Network Processor. When the
chip is powered up, bypass clock will be sent to all the units. After the PLL is locked, clock unit
will switch all units from bypass clock to a fixed frequency clock which is generated by dividing
PLL OUTPUT FREQUENCY by 16. Once Clock Control CSR is written, clock unit will replace
fixed frequency clock with the defined clocks for different units.
Table 148. Clock Rates Examples
Input Oscillator Frequency (MHz) 100
PLL Output Frequency (MHz)
[PLL Multiplier]
1
1. This multiplier is selected via SP_AD[5:0] strap pins.
2000
[20]
2200
[22]
2400
[24]
2600
[26]
2800
[28]
4000
[40]
4800
[48]
Microengine Frequency
2
2. This frequency is the PLL output frequency divided by 2.
1000 1100 1200 1300 1400 2000 2400
Intel XScale
®
core & Command/Push/Pull
Bus Frequency
3
3. This frequency is the PLL output frequency divided by 4.
500 550 600 650 700 1000 1200
Divide Ratio for other Units
(except APB)
4
4. The ABP divisor specified in the CLOCK_CONTROL CAP CSR is scaled by an additional x4.
Divisor
5
5. This divisor is selected via the CLOCK_CONTROL CAP CSR. The Base Frequency is the PLL output frequency divided by 2
2
6
6. This divide ratio is only used by test logic. In the normal functional mode, this ratio is reserved for Push/Pull clocks only.
500 550 600 650 700 1000 1200
3 333 367 400 433 467 666 800
4 250 275 300 325 350 500 600
5 200 220 240 260 280 400 480
6 167 183 200 217 233 334 400
7 143 157 171 186 200 286 342
8 125 138 150 163 175 250 300
9 111 122 133 144 156 222 266
10 100 110 120 130 140 200 240
11 91 100 109 118 127 182 218
12 83 92 100 108 117 166 200
13 77 85 92 100 107 154 184
14 71 79 86 93 100 142 172
15 67 73 80 87 93 134 160