Filter
Top Products
Hardware Reference Manual 203
Intel
®
IXP2800 Network Processor
DRAM
5.11.2 DRAM Push Arbiter Description
The general data flow for a push operation is as shown in Table 68. The DRAM Push Arbiter
functional blocks are shown in Figure 72.
The push arbiter takes push requests from any requestors. Each requestor has a dedicated request
FIFO. A request comes in the form of a PUSH_ID, and is accompanied by the data to be pushed, a
data error bit, and a chain bit. All of this information is enqueued in the correct FIFO for each
request, i.e., for each eight bytes of data. The push arbiter must drive a full signal to the requestor if
the FIFO reaches a predefined “full” level to apply backpressure and stop requests from coming.
The FIFO is 64 entries deep and goes full at 40 entries. The long skid allows for burst reads in
flight to finish before stalling the DRAM controller. If the FIFO is not full, the push arbiter can
enqueue a new request from each requestor on every cycle.
The push arbiter monitors the heads of each FIFO, and does a round robin arbitration between any
available requestors. If the chain bit is asserted, it indicates that once the head request of a queue is
granted, the arbiter should continue to grant that queue until the chain bit de-asserts. It is expected
that the requestor will assert the chain bit for no longer than a full burst length. The push arbiter
must also take special notice of requests destined for the receive buffer in the Media Switch Fabric
(MSF). Finally, the push arbiter must manage the delivery of data at different rates, depending on
how wide the bus is going into a given target.
The Microengines, PCI, and the Intel XScale
®
core all have 32-bit data buses. For these targets, the
push arbiter takes two clock cycles to deliver 64 bits of data by first delivering bits 31:0 in the first
cycle, and then putting bits 63:32 onto the low 32 bits of the PUSH_DATA in the second cycle.
Table 68. DRAM Push Arbiter Operation
Push Bus Master/Requestor Data Source Data Destination
IXP2800 Network Processor
D0 Unit
D1 Unit
D2 Unit
Current Master
TC0 Cluster (ME 0 – 7)
TC1 Cluster (ME 10 – 17)
Intel XScale
®
core
PCI Unit
MSF Unit