Filter
Top Products
Hardware Reference Manual 311
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
8.9.4.5 Implementation of a Bridge Chip to CSIX-L1
The Intel
®
IXP2800 Network Processor support for the CSIX-L1 protocol in the dual chip, full-
duplex configuration minimizes the difficulty in implementing a bridge chip to a standard CSIX-L1
interface. If dynamic de-skew training is not employed, the bridge chip can directly pass through
the different CSIX-L1 protocol elements, CFrames, and Dead Cycles. The horizontal parity must
be recalculated on each side of the bridge chip. If the standard CSIX-L1 interface implements a
CWord width that is greater than 32 bits, it must implement a synchronization mechanism for
aligning the received 32-bit portions of the CWord before passing the CWord to the network
processor.
For transmitting the standard CSIX-L1 interface, the bridge chip must assert the start-of-frame
signal for each 32-bit portion of the CWord, as the network processor only asserts it for the first
32-bit portion. If the bridge chip requires clock frequencies on the network processor interface and
the standard CSIX-L1 interface to be appropriate, exact multiples of each other (2x for 32-bit
CWord, 4x for 64-bit CWord, 6x for 96-bit CWord, and 8x for 128-bit CWord), then the bridge chip
requires only minimal buffering and does not need to implement any flow control mechanisms.
A slightly more complicated bridge allows incorporating dynamic de-skew training and/or
independent clock frequencies for the network processor and standard CSIX-L1 interfaces. The
bridge chip must implement a control and data FIFO for each direction and the link-level flow
control mechanisms specified in the protocol using CRdy and DRdy. The FIFOs must be large
enough to accommodate the response latency of the link-level flow control mechanisms.
Idle CFrames and Dead Cycles are not directly passed through this more complicated bridge chip,
but are discarded on reception and generated on transmission. The network processor interface of
this bridge chip can support the dynamic de-skew training protocol extensions implemented on the
network processor because it can send a training sequence to the network processor between
CFrames without regard to CFrames arriving over the standard CSIX-L1 interface. (In the simpler
bridge design, these CFrames must be forwarded immediately to the network processor.)