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68 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Technical Description
There is a Transmit Valid bit per element, that marks the element as ready to be transmitted.
Microengines move all data into the element, by either or both of
msf[write] and
dram[tbuf_wr] instructions to the TBUF. Microengines also write the element Transmit Control
Word with information about the element. When all of the data movement is complete, the
Microengine sets the element valid bit.
1. Move data into TBUF by either or both of
msf[write] and dram[tbuf_wr] instructions to
the TBUF.
2. Wait for 1 to complete.
3. Write Transmit Control Word at TBUF_ELEMENT_CONTROL_# address. Using this
address sets the Transmit Valid bit.
2.7.5 The Flow Control Interface
The MSF provides flow control support for SPI-4 and CSIX.
2.7.5.1 SPI-4
SPI-4 uses a FIFO Status Channel to provide flow control information. MSF receives the
information from the PHY device and stores it so that Microengines can read the information on a
per-port basis. It can then use that information to determine when to transmit data to a given port.
The MSF also sends status to the PHY based on the amount of available space in the RBUF —
i.e., done by hardware without Microengines.
2.7.5.2 CSIX
CSIX provides two types of flow control — link level and per queue.
• The link level control is handled by hardware. MSF will stop transmission is response to link
level flow control received from the Switch Fabric. MSF will assert link level flow control
based on the amount of available space in the RBUF.
• Per queue flow control information is put into the FCIFIFO and handled by Microengine
software. Also, if required, Microengines can send Flow Control CFrames to the Switch
Fabric under software control.
In both cases, for a full-duplex configuration, information is passed from the Switch Fabric to the
Egress IXP2800 Network Processor, which then passes it to the Ingress IXP2800 Network
Processor over a proprietary flow control interface.