Filter
Top Products
50 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Technical Description
2.4 DRAM
The IXP2800 Network Processor has controllers for three Rambus* DRAM (RDRAM) channels.
Each of the controllers independently accesses its own RDRAMs, and can operate concurrently
with the other controllers (i.e., they are not operating as a single, wider memory). DRAM provides
high-density, high-bandwidth storage and is typically used for data buffers.
• RDRAM sizes of 64, 128, 256, or 512 Mbytes, and 1 Gbyte are supported; however, each of
the channels must have the same number, size, and speed of RDRAMs populated. Refer to
Section 5.2 for supported size and loading configurations.
• Up to two Gbytes of DRAM is supported. If less than two Gbytes of memory is present, the
upper part of the address space is not used. It is also possible, for system cost and area savings,
to have Channels 0 and 1 populated with Channel 2 empty, or Channel 0 populated with
Channels 1and 2 empty.
• Reads and writes to RDRAM are generated by Microengines, The Intel XScale
®
core, and PCI
(external Bus Masters and DMA Channels). The controllers also do refresh and calibration
cycles to the RDRAMs, transparently to software.
• RDRAM Powerdown and Nap modes are not supported.
• Hardware interleaving (also known as striping) of addresses is done to provide balanced
access to all populated channels. The interleave size is 128 bytes. Interleaving helps to
maintain utilization of available bandwidth by spreading consecutive accesses to multiple
channels. The interleaving is done in the hardware in such a way that the three channels appear
to software as a single contiguous memory space.
• ECC (Error Correcting Code) is supported, but can be disabled. Enabling ECC requires that
x18 RDRAMs be used. If ECC is disabled x16 RDRAMs can be used. ECC can detect and
correct all single-bit errors, and detect all double-bit errors. When ECC is enabled, partial
writes (writes of less than 8 bytes) must be done as read-modify-writes.
2.4.1 Size Configuration
Each channel can be populated with anywhere from one-to-four RDRAMs (Short Channel Mode).
Refer to Section 5.2 for supported size and loading configurations. The RAM technology used will
determine the increment size and maximum memory per channel as shown in Table 9.
RDRAMs with 1 x 16 or 2 x 16 dependent banks, and 4 independent banks are supported.
Table 9. RDRAM Sizes
RDRAM Technology
1
Increment Size Maximum per Channel
64/72 MB 8 MB 256 MB
128/144 MB 16 MB 512 MB
256/288 MB 32 MB 1 GB
2
512/576 MB 64 MB 2 GB
2
NOTES:
1. The two numbers shown for each technology indicate x16 parts and x18 parts.
2. The maximum memory that can be addressed across all channels is 2 GB. This limitation is based on the
partitioning of the 4-GB address space (32-bit addresses). Therefore, if all three channels are used, each
can be populated up to a maximum of 768 MB. Two channels can be populated to a maximum of
1 GB each. A single channel can be populated to a maximum of 2 GB.