Filter
Top Products
78 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Technical Description
The access is asynchronous. Insertion of delay cycles for both data setup and hold time is
programmable via internal Control registers. The transfer can also wait for a handshake
acknowledge signal from the external device.
2.12 I/O Latency
Table 19 shows the latencies for transferring data between the Microengine and the other sub-
system components. The latency is measured in 1.4 GHz cycles.
2.13 Performance Monitor
The Intel XScale
®
core hardware provides two 32-bit performance counters that allow two unique
events to be monitored simultaneously. In addition, the Intel XScale
®
core implements a 32-bit
clock counter that can be used in conjunction with the performance counters; its sole purpose is to
count the number of core clock cycles, which is useful in measuring total execution time.
Table 19. I/O Latency
Sub-system
DRAM
(RDR)
SRAM
(QDR)
Scratch MSF
Transfer Size
8 bytes – 16 bytes
(note 2)
4 bytes 4 bytes 8 bytes
Average Read
Latency
~ 295 cycles
(note 3)
100 (light load) –
160 (heavy load)
~ 100 cycles
(range 53 – 152)
range 53 – 120
(RBUF)
Average Write
Latency
~ 53 cycles ~ 53 cycles ~ 40 cycles
~ 48 cycles
(TBUF)
Note1: RDR, QDR, MSF, and Scratch values are extracted from a simulation model.
Note 2: Minimum DRAM burst size on pins is 16 bytes. Transfers less than 16 bytes incur the same as a
16-byte transfer.
Note 3: At 1016 MHz, read latency should be ~ 240 cycles.