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118 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Intel XScale
®
Core
3.9.4.6 Status Register Access Instructions
3.9.4.7 Load/Store Instructions
3.9.4.8 Semaphore Instructions
Table 35. Status Register Access Instruction Timings
Mnemonic Minimum Issue Latency Minimum Result Latency
MRS 1 2
MSR 2 (6 if updating mode bits) 1
Table 36. Load and Store Instruction Timings
Mnemonic Minimum Issue Latency Minimum Result Latency
LDR 1 3 for load data; 1 for writeback of base
LDRB 1 3 for load data; 1 for writeback of base
LDRBT 1 3 for load data; 1 for writeback of base
LDRD 1 (+1 if Rd is R12) 3 for Rd; 4 for Rd+1; 2 for writeback of base
LDRH 1 3 for load data; 1 for writeback of base
LDRSB 1 3 for load data; 1 for writeback of base
LDRSH 1 3 for load data; 1 for writeback of base
LDRT 1 3 for load data; 1 for writeback of base
PLD 1 N/A
STR 1 1 for writeback of base
STRB 1 1 for writeback of base
STRBT 1 1 for writeback of base
STRD 2 1 for writeback of base
STRH 1 1 for writeback of base
STRT 1 1 for writeback of base
Table 37. Load and Store Multiple Instruction Timings
Mnemonic Minimum Issue Latency
1
1. LDM issue latency is 7 + N if R15 is in the register list and 2 + N if it is not. STM issue latency is calculated as 2 + N. N is
the number of registers to load or store.
Minimum Result Latency
LDM 3 – 23 1 – 3 for load data; 1 for writeback of base
STM 3 – 18 1 for writeback of base
Table 38. Semaphore Instruction Timings
Mnemonic Minimum Issue Latency Minimum Result Latency
SWP 5 5
SWPB 5 5