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Hardware Reference Manual 129
Intel
®
IXP2800 Network Processor
Intel XScale
®
Core
3.11.4.1 Summary of Rules for the Atomic Command Regarding I/O
The following rules summarize the Atomic command, regarding I/O.
• SWP to SRAM/Scratch and Not cbiIO, Xscale_IF generates an Atomic operation command.
• SWP to all other Addresses that are not SRAM/Scratch, will be treated as separate read and
write commands. No Atomic command is generated.
• SWP to SRAM/Scratch and cbiIO, will be treated as separate read and write commands. No
Atomic command is generated.
3.11.4.2 Intel XScale
®
Core Access to SRAM Q-Array
The Intel XScale
®
core can access the SRAM controllers queue function to do buffer allocation
and freeing. Allocation does a SRAM dequeue (deq) operation, and freeing does a SRAM enqueue
(enq) operation. Alias addresses are used as shown in Table 50 to access the freelist. Each SRAM
channel supports up to 64 lists, so there are 64 addresses per channel.
Address 7:2 selects which Queue_Array entry within the SRAM channel is used.
Doing a load to an address in the table will do a deq, and the SRAM controller returns the
dequeued information (i.e., the buffer pointer) as the load data; a store to an address in the table
will do an enq, and the data to be enqueued is taken from the Intel XScale
®
core store data.
The gasket generates command fields as follows, based on address and cbiLd:
Target_ID = SRAM (00 0010)
Command = deq (1011) if cbiLd, enq (1100) if ~cbiLd
Token[1:0] = 0x0
Byte_Mask = 0xFF
Length = 0x1
Address = {XScale_Address[23:22], XScale_Address[7:2], XScale_Write_Data[25:2]}
Note: On the command bus, address[31:30] selects the SRAM channel, address[29:24] is the Q_Array
number, and address[23:0] is the SRAM longword address. For Dequeue, the SRAM controller
ignores address[23:0].
Table 50. IXP2800 Network Processor SRAM Q-Array Access Alias Addresses
Channel Address Range
0 0xCC00 0100 – 0xCC00 01FC
1 0xCC40 0100 – 0xCC40 01FC
2 0xCC80 0100 – 0xCC80 01FC
3 0xCCC0 0100 – 0xCCC0 01FC