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150 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Intel XScale
®
Core
3.12.7.6.4 Single Read Transfer for a Self-Timing Device
Figure 41 demonstrates the single read transfer issued to a self-timing PROM device followed by
another write transaction. The CSR assumed to be programmed to the value of setup=4,
pulse width=0, and hold=2.
The only difference for self-timed mode is in the SP_ACK_L signal. It has a dominant effect on the
length of the transaction cycle or it overrides the value in the timing control register. A time-out
counter is set to 256. The SP_ACK_L should arrive before the time-out counter counts down to 0.
Similarly to the single write for self-timing device, an interrupt is launched for the time-out event
and the time-out register is updated. In this case, the data will be sampled at clock cycle 12.
3.12.7.7 SONET/SDH Microprocessor Access Support
To support the SONET/SDH Microprocessor Interface, extra logic is added into this unit. Here we
consider three SONET/SDH available components, including the Lucent* TDAT042G5,
PMC-Sierra* PM5351, Intel, and AMCC* SONET/SDH devices.
However, because these microprocessor interfaces are not standardized, we treat them separately
and a configuration register is installed to activate the bus to work with different interface protocol
at a time. Extra pins are also added to accomplish this task.
A microprocessor interface type register is used to provide these kinds of solutions. The user is
allowed to configure the interface to the following four different modes. The pin functionality and
the interface protocol will be changed accordingly. By default, it activates the mode 0 with 8-bit
generic PROM device support as mentioned above.
Figure 41. Mode 0 Single Read Transfer for a Self-Timing Device
A9709-01
SP_CLK
SP_ALE_L
SP_CS_L
[1:0]
SP_WR_L
D[7:0] D[7:0]
A[1:0]
24:1817:109:2 24:1817:109:2
SP_RD_L
SP_A[1:0]
SP_AD[7:0]
SP_ACK_L
20 4 6 8 10 12 14 16 18 20