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Hardware Reference Manual 365
Intel
®
IXP2800 Network Processor
Clocks and Reset
“reset_out_strap” is sampled as 0 on the trailing edge of reset, nRESET_OUT is de-asserted based
on the value of IXP_RESET_0[15] which is written by software. If “reset_out_strap” is sampled as
1 on the trailing edge of reset, nRESET_OUT is de-asserted after PLL locks.
During normal function mode, if software wants to pull nRESET_OUT high, it should set
IXP_RESET_0[22] = 1 and then set IXP_RESET_0[15] = 1. To pull nRESET_OUT low, software
should set the IXP_RESET_0[15] bit back to 0.
Figure 133. Reset Out Behavior
A9780-01
PLL
Lock Signal
EXTRST_EN
RESET_OUT
RESET_OUT_STRAP
0
1
1
0
EXTRST
IXP_RESET0
Register
[15]
[22]