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Hardware Reference Manual 279
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
The TXCSRB and RXCSRB pins are not used in Simplex Mode. The RXCFC and TXCFC pins are
used for flow control in both Simplex and Duplex Modes. The Egress IXP2800 Network Processor
uses the TXCSOF, TXCDAT, and TXCPAR pins to send CFrames to the Switch Fabric.
The Ingress IXP2800 Network Processor uses the RXCSOF, RXCDAT, and RXCPAR pins to
receive CFrames from the Switch Fabric (the Switch Fabric is expected to send Flow Control
CFrames on these pins instead of the RDAT pins in Simplex Mode). The
FC_Ingress_Status[SF_CReady] and FC_Ingress_Status[SF_DReady] bits are set are from the
“Ready bits” received in all incoming CFrames received on this interface. Transmit hardware in the
Ingress IXP2800 Network Processor uses the FC_Ingress_Status[SF_CReady] and
FC_Ingress_Status[SF_DReady] bits to flow control the data and control transmit on TDAT.
CFrames in the FCIFIFO of the Ingress IXP2800 Network Processor are read by Microengines,
which use them to keep current VOQ Flow Control information (this is the same as for Full Duplex
Mode). The FCI_Not_Empty and FCI_Full status flags, as described in Section 8.5.2.1 let the
Microengine know if the FCIFIFO has any CWords in it. When FCI_Full is asserted,
FC_Ingress_Status[TM_CReady] will be deasserted; that bit is put into the Ready field of
CFrames going to the Switch Fabric, to inform it to stop sending Control CFrames.
Flow Control CFrames to the Switch Fabric are put into FCEFIFO, instead of TBUF, as in the Full
Duplex Mode case. In this mode, the Microengines create CFrames and write them into FCEFIFO
using the
msf[write] instruction to the FCEFIFO address; the length of the write can be from
1 – 16. The Microengine creating the CFrame must put a header (conforming to CSIX Base Header
format) in front of the message, indicating to the hardware how many bytes to send.
The Microengine first tests if there is room in FCEFIFO by reading the
FC_Egress_Status[FCEFIFO_Full] status bit. After the CFrame has been written to FCEFIFO,
the Microengine writes to the FCEFIFO_Validate register, indicating that the CFrame should be
sent out on TXCDAT; this prevents underflow by ensuring that the entire CFrame is in FCEFIFO
before it can be transmitted. A validated CFrame at the head of FCEFIFO is started on TXCDAT if
FC_Egress_Status[SF_CReady] is asserted, and held off, if it is deasserted. However, once
started, the entire CFrame is sent, regardless of changes in FC_Egress_Status[SF_CReady].
The FC_Egress_Status[SF_DReady] is ignored in controlling FCEFIFO.
FC_Egress_Status[TM_CReady] and FC_Egress_Status[TM_DReady] are placed by hardware
into the Base Header of outgoing CFrames. Horizontal and Vertical parity are created by hardware.
If there is no valid CFrame in FCEFIFO, or if FC_Egress_Status[SF_CReady] is deasserted, then
idle CFrames are sent on TXCDAT. The idle CFrames also carry (in the Base Header Ready Field),
both FC_Egress_Status[TM_CReady] and FC_Egress_Status[TM_DReady]. In all cases, the
Switch Fabric must honor the “ready bits” to prevent overflowing RBUF.
Note: For simplex mode, there is a condition in which the Flow Control Bus may take too long to
properly control incoming traffic on CSIX. This condition may occur when large packets are
transmitted on the Flow Control Bus and small packets are transmitted on CSIX. For example, this
condition may occur if the Switch Fabric’s CSIX Receive FIFO is full, and the FIFO wants to
deassert the x_RDY bit, but a maximum-sized flow control CFrame just went out. The Flow
Control Bus is a 4-bit wide LVDS interface that sends data on both the rising and falling edges of
the clock. As such, it takes 260 clock cycles to transmit a maximum-sized CFrame, which consists
of 256 bytes, plus a 4-byte base header/vertical parity (i.e, 260 bytes total). The interface does not
see the transition of the X_RDY bit until this CFrame has been transmitted or until 260 cycles later.