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352 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
PCI Unit
9.5.3.3 Master from the Intel XScale
®
Core or Microengine Transfer
(Write to PCI) Receives PCI_PERR_L on PCI Bus
1. If PCI_CMD_STAT[PERR_RESP] is not set, PCI Unit will ignore the parity error.
2. If PCI_CMD_STAT[PERR_RESP] is set:
a. Core sets PCI_CMD_STAT[PERR].
b. Master Interface sets PCI_CONTROL[DPE] which will interrupt the Intel XScale
®
core
if enabled.
9.5.3.4 Master Read from PCI (Read from PCI) Has Bad Data Parity
1. If PCI_CMD_STAT[PERR_RESP] is not set, PCI Unit will ignore the parity error.
2. If PCI_CMD_STAT[PERR_RESP] is set:
a. Core asserts PCI_PERR_L on PCI.
b. Master Interface sets PCI_CONTROL[DPED] which will interrupt the Intel XScale
®
core
if enabled.
c. Data that has been read from PCI is sent to the Intel XScale
®
core or Microengine with a
data error indication.
9.5.3.5 Master Transfer Receives PCI_SERR_L from the PCI Bus
Master Interface sets PCI_CONTROL[RSERR] which will interrupt the Intel XScale
®
core if
enabled.
9.5.3.6 Intel XScale
®
Core Microengine Requests Direct Transfer when
the PCI Bus is in Reset
Master Interface will complete the transfer and drop the write data and return all ones on the read
data.
9.6 PCI Data Byte Lane Alignment
During any endian conversion, PCI does not need to do any longword swapping between two
32-bit longwords (LW1, LW0). But PCI may need to do byte swapping within the 32-bit
longwords. Because of the different endian convention between PCI Bus and the memory, all data
going between the PCI core FIFO and memory data bus passes through the byte lane reversal as
shown in Table 130 through Table 137.
PCI allows byte-enable swapping only without the data swapping or allow data swapping only
without byte enable swapping. When PCI handle the mis align data in above two cases, PCI will
only care about valid data. So PCI will drive any data values for those mis-aligned invalid data
portions.