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Hardware Reference Manual 293
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
SPI-4.2 supports up to 256 port addresses, with independent flow control for each. For data
received by the PHY and passed to the link layer device, flow control is optional. The flow control
mechanism is based upon independent pools of credits, corresponding to 16-byte blocks, for each
port.
The CSIX-L1 protocol supports 4096 ports and 256 unicast classes of traffic. It supports various
forms of multicast and 256 multicast queues of traffic. The protocol supports independent link-
level flow control for data and control traffic and supports virtual output queue (VOQ) flow control
for data traffic.
8.9.1 Receiver and Transmitter Configurations
The network processor receiver and transmitter independently support three different
configurations:
• Simplex (SPI-4.2 or CSIX-L1 protocol), described in Section 8.9.1.1.
• Hybrid simplex (transmitter only, SPI-4.2 data path, and CSIX-L1 protocol flow control),
described in Section 8.9.1.2.
• Dual Network Processor, full duplex (CSIX-L1 protocol), described in Figure 8.9.1.3.
Additionally, the combined receiver and transmitter support a single Network Processor, full-
duplex configuration using two different protocols:
• Multiplexed SPI-4.2 protocol, described in Section 8.9.1.4.
• CSIX-L1 protocol, described in Section 8.9.1.5.
In both the simplex and hybrid simplex configurations, the path receiving from a framer, fabric, or
Network Processor is independent of the path transmitting to a framer, fabric, or Network
Processor. In a full duplex configuration, the receiving path forwards CSIX-L1 control information
for the transmit path and vice versa.
8.9.1.1 Simplex Configuration
In the simplex configuration, as shown in Figure 102, the reverse path provides control information
to the transmitter. This control information may include flow control information and requests for
dynamic training sequences.
Figure 102. Simplex Configuration
B2735-01
Transmitter
Forward Path
(18 to 20 Signals)
Reverse Path
(3 to 7 Signals)
Receiver