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348 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
PCI Unit
9.5 PCI Unit Error Behavior
9.5.1 PCI Target Error Behavior
9.5.1.1 Target Access Has an Address Parity Error
1. If PCI_CMD_STAT[PERR_RESP] is not set, PCI Unit will ignore the parity error.
2. If PCI_CMD_STAT[PERR_RESP] is set:
a. PCI core will not claim the cycle regardless of internal device select signal.
b. PCI core will let the cycle terminate with master abort.
c. PCI core will not assert PCI_SERR_L.
d. Slave Interface sets PCI_CONTROL[TGT_ADR_ERR], which will interrupt the Intel
XScale
®
core if enabled.
9.5.1.2 Initiator Asserts PCI_PERR_L in Response to One of Our Data
Phases
1. Core does nothing.
2. Responsibility lies with the initiator to discard data, report this to the system, etc.
9.5.1.3 Discard Timer Expires on a Target Read
1. PCI unit discards the read data.
2. PCI Unit invalidates the delayed read address
3. PCI Unit sets Discard Timer Expired bit (DTX) in the PCI_CONTROL.
4. If enabled (XSCALE_INT_ENABLE [DTE]), the PCI unit interrupts the Intel XScale
®
core.
9.5.1.4 Target Access to the PCI_CSR_BAR Space Has Illegal
Byte Enables
Note: The acceptable byte enables are:
1. PCI local CSRs - PCI_BE[3:0] = 0x0or 0xF.
2. CSRs not in the PCI Unit - PCI_BE[3:0] = 0x0, 0xE, 0xD, 0xB, 0x7, 0xC, 0x3, or 0xF.
When byte-enables are detected, the hardware asserts the following error conditions:
1. Slave Interface will set PCI_CONTROL[TGT_CSR_BE].
2. Slave Interface will issue target abort for target read and drop the transaction for target write.