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76 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Technical Description
2.10 Control and Status Register Access Proxy
The Control and Status Register Access Proxy (CAP) contains a number of chip-wide control and
status registers. Some provide miscellaneous control and status, while others are used for inter-
Microengine or Microengine to the Intel XScale
®
core communication (note that rings in
Scratchpad Memory and SRAM can also be used for inter-process communication). These include:
• INTERTHREAD SIGNAL — Each thread (or context) on a Microengine can send a signal to
any other thread by writing to InterThread_Signal register. This allows a thread to go to sleep
waiting completion of a task by a different thread.
• THREAD MESSAGE — Each thread has a message register where it can post a software-
specific message. Other Microengine threads, or the Intel XScale
®
core, can poll for
availability of messages by reading theTHREAD_MESSAGE_SUMMARY register. Both the
THREAD_MESSAGE and corresponding THREAD_MESSAGE_SUMMARY clear upon a
read of the message; this eliminates a race condition when there are multiple message readers.
Only one reader will get the message.
• SELF DESTRUCT — This register provides another type of communication. Microengine
software can atomically set individual bits in the SELF_DESTRUCT registers; the registers
clear upon read. The meaning of each bit is software-specific. Clearing the register upon read
eliminates a race condition when there are multiple readers.
• THREAD INTERRUPT — Each thread can interrupt the Intel XScale
®
core on two different
interrupts; the usage is software-specific. Having two interrupts allows for flexibility, for
example, one can be assigned to normal service requests and one can be assigned to error
conditions. If more information needs to be associated with the interrupt, mailboxes or Rings
in Scratchpad Memory or SRAM could be used.
• REFLECTOR — CAP provides a function (called “reflector”) where any Microengine thread
can move data between its registers and those of any other thread. In response to a single write
or read instruction (with the address in the specific reflector range) CAP will get data from the
source Microengine and put it into the destination Microengine. Both the sending and
receiving threads can optionally be signaled upon completion of the data movement.
2.11 Intel XScale
®
Core Peripherals
2.11.1 Interrupt Controller
The Interrupt Controller provides the ability to enable or mask interrupts from a number of chip
wide sources, for example:
• Timers (normally used by Real-Time Operating System).
• Interrupts generated by Microengine software to request services from the Intel XScale
®
core.
• External agents such as PCI devices.
• Error conditions, such as DRAM ECC error, or SPI-4 parity error.
Interrupt status is read as memory mapped registers; the state of an interrupt signal can be read
even if it is masked from interrupting. Enabling and masking of interrupts is done as writes to
memory mapped registers.