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134 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Intel XScale
®
Core
3.12 Intel XScale
®
Core Peripheral Interface
This section describes the Intel XScale
®
core Peripheral Interface unit (XPI). The XPI is the block
that connects to all the slow and serial interfaces that communicate with the Intel XScale
®
core
through the APB. These can also be accessed by the Microengines and PCI unit.
This section does not describe the Intel XScale
®
core interface protocol, only how to interface with
the peripheral devices connected to the core. The I/O units described are:
• UART
• Watchdog timers
• GPIO
• Slowport
All the peripheral units are memory mapped from the Intel XScale
®
core point of view.
3.12.1 XPI Overview
Figure 30 shows the XPI location in the IXP2800 Network Processor. The XPI receives read and
write commands from the Command Push Pull bus to addresses the memory has mapped to I/O
devices.
The SHaC (Scratchpad, Hash Unit, and CSRs) acts like a bridge to control the access from the Intel
XScale
®
core or other host (like the PCI Unit). The extended APB is used to communicate between
the XPI and the SHaC. The extended APB has only one signal, APB_RDY, added. This signal is
used to tell the SHaC when the transaction should be terminated.
The XPI is responsible for passing the data between the extended APB and the internal blocks, like
the UART, GPIO, Timer, and Slowport, which will in turn pass these data to an external peripheral
device with a corresponding bus format.
The XPI is always a master on the Slowport bus and all the Slowport devices act like slaves. On the
other side, the SHaC is always the master and the XPI is the slave with respect to the APB.