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390 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Performance Monitor Unit
26 TURNA0_C_P APB_CLK single separate
It enters the termination state of the state machine 0
for the mode 0 of Slowport.
27 IDLE1_0_P APB_CLK single separate
It displays the idle state of the state machine 1 for the
mode 1 of Slowport.
28 START1_1_P APB_CLK single separate
It enters the start state of the state machine 1 for the
mode 1 of Slowport.
29 ADDR11_3_P APB_CLK single separate
It enters the first address state, AD[7:0], of the state
machine 1 for the mode 1 of Slowport.
30 ADDR21_2_P APB_CLK single separate
It enters the second address state, AD[15:8], of the
state machine 1 for the mode 1 of Slowport.
31 ADDR31_6_P APB_CLK single separate
It enters the second address state, AD[23:16], of the
state machine 1 for the mode 1 of Slowport.
32 ADDR41_7_P APB_CLK single separate
It enters the second address state, AD[24], of the
state machine 1 for the mode 1 of Slowport.
33 WRDATA1_5_P APB_CLK single separate
It unpacks the data from the APB onto the Slowport
bus for the state machine 1 for the mode 1 of
Slowport.
34 PULW1_4_P APB_CLK single separate
It enters the pulse width of the data transaction cycle
for the state machine 1 for the mode 1 of Slowport.
35 CHPSEL1_C_P APB_CLK single separate
It enters the chip select assertion pulse width when
the state machine 1 is active for the mode 1 of
Slowport.
36 OUTEN1_E_P APB_CLK single separate
It enters the cycle when the OE is asserted during
running on the state machine 1 for the mode 1 of
Slowport.
37 PKDATA1_F_P APB_CLK single separate
It enters the read data packing state when the state
machine 1 is active for the mode 1 of Slowport.
38 LADATA1_D_P APB_CLK single separate
It enters the data capturing cycle when the state
machine 1 is active for the mode 1 of Slowport.
39 READY1_9_P APB_CLK single separate
It enters the acknowledge state to terminate the read
cycle when the state machine 1 is active for the mode
1 of Slowport.
40 TURNA1_8_P APB_CLK single separate
It enters the turnaround state of the transaction when
the state machine 1 is active for the mode 1 of
Slowport.
41 IDLE2_0_P APB_CLK single separate
It displays the idle state of the state machine 2 for the
mode 2 of Slowport.
42 START2_1_P APB_CLK single separate
It enters the start state of the state machine 2 for the
mode 2 of Slowport.
43 ADDR12_3_P APB_CLK single separate
It enters the first address state, AD[7:0], of the state
machine 2 for the mode 2 of Slowport.
44 ADDR22_2_P APB_CLK single separate
It enters the second address state, AD[15:8], of the
state machine 2 for the mode 2 of Slowport.
45 ADDR32_6_P APB_CLK single separate
It enters the second address state, AD[23:16], of the
state machine 2 for the mode 2 of Slowport.
46 ADDR42_7_P APB_CLK single separate
It enters the second address state, AD[24], of the
state machine 2 for the mode 2 of Slowport.
47 WRDATA2_5_P APB_CLK single separate
It unpacks the data from the APB onto the Slowport
bus for the state machine 2 for the mode 2 of
Slowport.
Table 155. XPI PMU Event List (Sheet 2 of 4)