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User’s Manual
PPC440x5 CPU Core Preliminary
Page 104 of 589
cache.fm.
September 12, 2002
The ICC also handles the execution of the PowerPC instruction cache management instructions, for touching
(prefetching) or invalidating cache lines, or for flash invalidation of the entire cache. Resources for controlling
and debugging the instruction cache operation are also provided.
The rest of this section describes each of these functions in more detail.
4.2.1 ICC Operations
When the ICC receives an instruction fetch request from the instruction unit of the PPC440x5 core, the ICC
simultaneously searches the instruction cache array for the cache line associated with the virtual address of
the fetch request, and translates the virtual address into a real address (see Memory Management on
page 133 for information about address translation). If the requested cache line is found in the array (a cache
hit), the pair of instructions at the requested address are returned to the instruction unit. If the requested
cache line is not found in the array (a cache miss), the ICC sends a request for the entire cache line (32
bytes) to the instruction PLB interface, using the real address. Note that the entire 32-bytecache line is
requested, even if the caching inhibited (I) storage attribute is set for the memory page containing that cache
line (see Caching Inhibited (I) on page 145). Also note that the request to the instruction PLB interface is sent
using the specific instruction address requested by the instruction unit, so that the memory subsystem may
read the cache line target word first (if it supports such operation) and supply the requested instructions
before retrieving the rest of the cache line.
As the ICC receives each portion of the cache line from the instruction PLB interface, it is placed into the
instruction cache line fill data (ICLFD) buffer. Instructions from this buffer may be bypassed to the instruction
unit as requested, without waiting for the entire cache line to be filled. Once the entire cache line has been
filled into the buffer, and assuming that the memory page containing that line is cacheable, it is written into the
instruction cache. If the memory page containing the line is caching inhibited, the line will remain in the ICLFD
until it is displaced by a subsequent request for another cache line (either cachable or caching inhibited).
If a memory subsystem error (such as an address time-out, invalid address, or some other type of hardware
error external to the PPC440x5 core) occurs during the filling of the cache line, the line will not be written into
the instruction cache, although instructions from the line may still be forwarded to the instruction unit from the
ICLFD. Later, if execution of an instruction from that line is attempted, an Instruction Machine Check excep-
tion will be reported, and a Machine Check interrupt (if enabled) will result. See Machine Check Interrupt on
page 178 for more information on Machine Check interrupts.
Once a request for a cache line read has been requested on the instruction PLB interface, the entire line read
will be performed and the line will be written into the instruction cache (assuming no error occurs on the read),
regardless of whether or not the instruction stream branches (or is interrupted) away from the line being read.
This behavior is due to the nature of the PLB architecture, and the fact that once started, a cache line read
request type cannot be abandoned. This does not mean, however, that the ICC will wait for this cache line
read to complete before responding to a new request from the instruction unit (due, perhaps, to a branch redi-
rection, or an interrupt). Instead, the ICC will immediately access the cache to determine if the cache line at
the new address requested by the instruction unit is already in the cache. If so, the requested pair of instruc-
tions from this line will immediately be forwarded to the instruction unit, while the ICC in parallel continues to
fill the previously requested cache line. In other words, the instruction cache is completely non-blocking.
If the newly requested cache line is instead a miss in the instruction cache, the ICC will immediately attempt
to cancel the previous cache line read request. If the previous cache line read request has not yet been
requested on the PLB bus, the old request will be cancelled and the new request will be made. If the previous
cache line read request has already been requested, then as previously stated it cannot be abandoned, but