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dcbf
Data Cache Block Flush
PPC440x5 CPU Core User’s Manual Preliminary
Page 296 of 589
instrset.fm.
September 12, 2002
dcbf
Data Cache Block Flush
EA ← (RA|0) + (RB)
DCBF(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 if the RA field is 0 and is the contents of register RA otherwise.
If the data block corresponding to the EA is in the data cache and marked as modified (stored into), the data
block is copied back to main storage and then marked invalid in the data cache. If the data block is not
marked as modified, it is simply marked invalid in the data cache. The operation is performed whether or not
the memory page referenced by the EA is marked as cacheable.
If the data block at the EA is not in the data cache, no operation is performed.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Exceptions
This instruction is considered a “load” with respect to Data Storage exceptions. See Data Storage Interrupt on
page 181 for more information.
This instruction is considered a “store” with respect to data address compare (DAC) Debug exceptions. See
Debug Interrupt on page 195 for more information.
This instruction may cause a Cache Locking type of Data Storage exception. See Data Storage Interrupt on
page 181 for more information.
dcbf RA, RB
31 RA RB 86
0 6 11 16 21 31