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dcbt
Data Cache Block Touch
Preliminary PPC440x5 CPU Core User’s Manual
instrset.fm.
September 12, 2002 Page 299 of 589
dcbt
Data Cache Block Touch
EA ← (RA|0) + (RB)
DCBT(EA)
An effective address (EA) is formed by adding an index to a base address. The index is the contents of
register RB. The base address is 0 when the RA field is 0, and is the contents of register RA otherwise.
If the data block at the EA is not in the data cache and the memory page referenced by the EA is marked as
cacheable, the block is read from main storage into the data cache.
If the data block at the EA is in the data cache, or if the memory page referenced by the EA is marked as
caching inhibited, no operation is performed.
This instruction is not allowed to cause Data Storage interrupts nor Data TLB Error interrupts. If execution of
the instruction causes either of these types of exception, then no operation is performed, and no interrupt
occurs.
If instruction bit 31 contains 1, the contents of CR[CR0] are undefined.
Registers Altered
• None
Invalid Instruction Forms
• Reserved fields
Programming Notes
The dcbt instruction allows a program to begin a cache block fetch from main storage before the program
needs the data. The program can later load data from the cache into registers without incurring the latency of
a cache miss.
Exceptions
This instruction is considered a “load” with respect to Data Storage exceptions. See Data Storage Interrupt on
page 181 for more information.
This instruction is considered a “load” with respect to data address compare (DAC) Debug exceptions. See
Debug Interrupt on page 195 for more information.
dcbt RA, RB
31 RA RB 278
0 6 11 16 21 31