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User’s Manual
PPC440x5 CPU Core Preliminary
Page 46 of 589
prgmodel.fm.
September 12, 2002
• For word loads and stores (including load/store multiple), bytes are reversed within the word, for one byte
order with respect to the other.
• For doubleword loads and stores (AP loads/stores only), bytes are reversed within the doubleword, for
one byte order with respect to the other.
• For quadword loads and stores (AP loads/stores only), bytes are reversed within the quadword, for one
byte order with respect to the other.
Note that this mechanism applies independent of the alignment of data. In other words, when loading a multi-
byte data operand with a scalar load instruction, bytes are accessed from the data cache (or memory) starting
with the byte at the calculated effective address and continuing with consecutively higher-numbered bytes
until the required number of bytes have been retrieved. Then, the bytes are arranged such that either the byte
from the highest-numbered address (for big endian storage regions) or the lowest-numbered address (for
little endian storage regions) is placed into the least-significant byte of the register. The rest of the register is
filled in corresponding order with the rest of the accessed bytes. An analogous procedure is followed for
scalar store instructions.
For load/store multiple instructions, each group of four bytes is transferred between memory and the register
according to the procedure for a scalar load word instruction.
For load/store string instructions, the most-significant byte of the first register is transferred to or from memory
at the starting (lowest-numbered) effective address, regardless of byte ordering. Subsequent register bytes
(from most-significant to least-significant, and then moving into the next register, starting with the most-signif-
icant byte, and so on) are transferred to or from memory at sequentially higher-numbered addresses. This
behavior for byte strings ensures that if two strings are loaded into registers and then compared, the first
bytes of the strings are treated as most significant with respect to the comparison.
2.1.3.4 Byte-Reverse Instructions
PowerPC Book-E defines load/store byte-reverse instructions which can access storage which is specified as
being of one byte ordering in the same manner that a regular (that is, non-byte-reverse) load/store instruction
would access storage which is specified as being of the opposite byte ordering. In other words, a load/store
byte-reverse instruction to a big endian memory page transfers data between the data cache (or memory)
and the register in the same manner that a normal load/store would transfer the data to or from a little endian
memory page. Similarly, a load/store byte-reverse instruction to a little endian memory page transfers data
between the data cache (or memory) and the register in the same manner that a normal load/store would
transfer the data to or from a big endian memory page.
The function of the load/store byte-reverse instructions is useful when a particular memory page contains a
combination of data with both big endian and little endian byte ordering. In such an environment, the Endian
storage attribute for the memory page would be set according to the predominant byte ordering for the page,
and the normal load/store instructions would be used to access data operands which used this predominant
byte ordering. Conversely, the load/store byte-reverse instructions would be used to access the data oper-
ands which were of the other (less prevalent) byte ordering.
Software compilers cannot typically make general use of the load/store byte-reverse instructions, so they are
ordinarily used only in special, hand-coded device drivers.