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User’s Manual
PPC440x5 CPU Core Preliminary
Page 222 of 589
debug.fm.
September 12, 2002
8.3.1 Instruction Address Compare (IAC) Debug Event
IAC debug events occur when execution is attempted of an instruction for which the instruction address and
other parameters match the IAC conditions specified by DBCR0, DBCR1, and the IAC registers. There are
four IAC registers on the PPC440x5, IAC1–IAC4. Depending on the IAC mode specified by DBCR1, these
IAC registers can be used to specify four independent, exact IAC addresses, or they can be configured in
pairs (IAC1/IAC2 and IAC3/IAC4) in order to specify ranges of instruction addresses for which IAC debug
events should occur.
8.3.1.1 IAC Debug Event Fields
There are several fields in DBCR0 and DBCR1 which are used to specify the IAC conditions, as follows:
IAC Event Enable Field
DBCR0[IAC1, IAC2, IAC3, IAC4] are the individual IAC event enables for each of the four IAC
events: IAC1, IAC2, IAC3, and IAC4. For a given IAC event to occur, the corresponding IAC
event enable bit in DBCR0 must be set. When a given IAC event occurs, the corresponding
DBSR[IAC1, IAC2, IAC3, IAC4] bit is set.
IAC Mode Field
DBCR1[IAC12M, IAC34M] control the comparison mode for the IAC1/IAC2 and IAC3/IAC4
events, respectively. There are three comparison modes supported by the PPC440x5:
• Exact comparison mode (DBCR1[IAC12M/IAC34M] = 0b00)
In this mode, the instruction address is compared to the value in the corresponding IAC register, and
the IAC event occurs only if the comparison is an exact match.
• Range inclusive comparison mode (DBCR1[IAC12M/IAC34M] = 0b10)
In this mode, the IAC1 or IAC2 event occurs only if the instruction address is within the range defined
by the IAC1 and IAC2 register values, as follows: IAC1 ≤ address < IAC2. Similarly, the IAC3 or IAC4
event occurs only if the instruction address is within the range defined by the IAC3 and IAC4 register
values, as follows: IAC3 ≤ address < IAC4.
For a given IAC1/IAC2 or IAC3/IAC4 pair, when the instruction address falls within the specified
range, either one or both of the corresponding IAC debug event bits will be set in the DBSR, as deter-
mined by which of the two corresponding IAC event enable bits are set in DBCR0. For example,
when the IAC1/IAC2 pair are set to range inclusive comparison mode, and the instruction address
falls within the defined range, then DBCR1[IAC1, IAC2] will determine whether one or the other or
both of DBSR[IAC1, IAC2] are set. It is a programming error to set either of the IAC pairs to a range
comparison mode (either inclusive or exclusive) without also enabling at least one of the correspond-
ing IAC event enable bits in DBCR0.
Instruction Complete (ICMP) Caused by the successful completion of the execution of any instruction.
Interrupt (IRPT) Caused by the generation of an interrupt.
Unconditional (UDE)
Caused by the assertion of an unconditional debug event request from the JTAG inter-
face to the PPC440x5 core.
Table 8-1. Debug Events
Event Description