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RSTCFG
Reset Configuration
Preliminary PPC440x5 CPU Core User’s Manual
regsumm440core.fm.
September 12, 2002 Page 509 of 589
RSTCFG
SPR 39B Supervisor Read-Only
See Reset Configuration (RSTCFG) on page 79.
Figure 10-41. Reset Configuration
0:15 Reserved
16 U0
U0 Storage Attribute
0 U0 storage attribute is disabled
1 U0 storage attribute is enabled
See Table 5-1 on page 135.
17 U1
U1 Storage Attribute
0 U1 storage attribute is disabled
1 U1 storage attribute is enabled
See Table 5-1 on page 135.
18 U2
U2 Storage Attribute
0 U2 storage attribute is disabled
1 U2 storage attribute is enabled
See Table 5-1 on page 135.
19 U3
U3 Storage Attribute
0 U3 storage attribute is disabled
1 U3 storage attribute is enabled
See Table 5-1 on page 135.
20:23 Reserved
24 E
E Storage Attribute
0 Accesses to the page are big endian.
1 Accesses to the page are little endian.
25:27 Reserved
28:31 ERPN Extended Real Page Number
This TLB field is prepended to the translated
address to form a 36-bit real address. See Table
5.4 Address Translation on page 140 and Table
5-3 Page Size and Real Address Formation on
page 142.
0 15 16 17 18 19 20 23 24 25 27 28 31
U0
U1
U2
U3
E
ERPN