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User’s Manual
PPC440x5 CPU Core Preliminary
Page 144 of 589
mmu.fm.
September 12, 2002
• dcbz instructions are treated as stores with respect to access control since they actually change the data
in a cache block. As such, they can cause Write Access Control exception type Data Storage interrupts.
• dcbi instructions are treated as stores with respect to access control since they can change the value of
a storage location by invalidating the “current” copy of the location in the data cache, effectively “restor-
ing” the value of the location to the “former” value which is contained in memory. As such, they can cause
Write Access Control exception type Data Storage interrupts.
• dcba instructions are treated as no-ops by the PPC440x5 under all circumstances, and thus can not
cause any form of Data Storage interrupt.
• icbi instructions are treated as loads with respect to access control. As such, they can cause Read
Access Control exception type Data Storage interrupts. Note that this instruction may cause a Data Stor-
age interrupt (and not an Instruction Storage interrupt), even though it otherwise would perform its opera-
tion on the instruction cache. Instruction storage interrupts are associated with exceptions which occur
upon the fetch of an instruction, whereas Data storage interrupts are associated with exceptions which
occur upon the execution of a storage access or cache management instruction.
• dcbt, dcbtst, and icbt instructions are treated as loads with respect to access control. As such, they can
cause Read Access Control exceptions. However, because these instructions are intended to act merely
as “hints” that the specified cache block will likely be accessed by the processor in the near future, such
exceptions will not result in a Data Storage interrupt. Instead, if a Read Access Control exception occurs,
the instruction is treated as a no-op.
• dcbf and dcbst instructions are treated as loads with respect to access control. As such, they can cause
Read Access Control exception type Data Storage interrupts. Flushing or storing a dirty line from the
cache is not considered a store since an earlier store operation has already updated the cache line, and
the dcbf or dcbst instruction is simply causing the results of that earlier store operation to be propagated
to memory.
• dccci and iccci instructions do not even generate an address, nor are they affected by the access control
mechanism. They are privileged instructions, and if executed in supervisor mode they will flash invalidate
the entire associated cache.
Table 5-4 summarizes the effect of access control on each of the cache management instructions.
Table 5-4. Access Control Applied to Cache Management Instructions
Instruction
Read
Protection
Violation
Exception?
Write
Protection
Violation
Exception?
dcba
No No
dcbf
Yes No
dcbi
No Yes
dcbst
Yes No
dcbt
Yes
1
No
dcbtst
Yes
1
No
dcbz
No Yes
dccci
No No
icbi
Yes No