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User’s Manual
PPC440x5 CPU Core Preliminary
Page 124 of 589
cache.fm.
September 12, 2002
4.3.1.7 Storage Access Ordering
In general, the DCC can perform load and store operations out-of-order with respect to the instruction stream.
That is, the memory accesses associated with a sequence of load and store instructions may be performed in
memory in an order different from that implied by the order of the instructions. For example, loads can be
processed ahead of earlier stores, or stores can be processed ahead of earlier loads. Also, later loads and
stores that hit in the data cache may be processed before earlier loads and stores that miss in the data
cache.
The DCC does enforce the requirements of the SEM, such that the net result of a sequence of load and store
operations is the same as that implied by the order of the instructions. This means, for example, that if a later
load reads the same address written by an earlier store, the DCC guarantees that the load will use the data
written by the store, and not the older “pre-store” data. But the memory subsystem could still see a read
access associated with an even later load before it sees the write access associated with the earlier store.
If the DCC needs to make a read request to the data read PLB interface, and this request conflicts with (that
is, references one or more of the same bytes as) an earlier write request which is being made to the data
write PLB interface, the DCC will withhold the read request from the data read PLB interface until the write
request has been acknowledged on the data write PLB interface. Once the earlier write request has been
acknowledged, the read request will be presented, and it is the responsibility of the PLB subsystem to ensure
that the data returned for the read request reflects the value of the data written by the write operation.
Conversely, if a write request conflicts with an earlier read request, the DCC will withhold the write request
until the read request has been acknowledged, at which point it is the responsibility of the PLB subsystem to
ensure that the data returned for the read request does not reflect the newer data being written by the write
request.
The PPC440x5 core provides storage synchronization instructions to enable software to control the order in
which the memory accesses associated with a sequence of instructions are performed. See Storage
Ordering and Synchronization on page 84 for more information on the use of these instructions.
4.3.2 Data Cache Coherency
The PPC440x5 core does not enforce the coherency of the data cache with respect to alterations of memory
performed by entities other than the PPC440x5 core. Similarly, if entities other than the PPC440x5 core
attempt to read memory locations which currently exist within the PPC440x5 core data cache and in a modi-
fied state, the PPC440x5 core does not recognize such accesses and thus will not respond to such accesses
with the modified data from the cache. In other words, the data cache on the PPC440x5 core is not a
snooping data cache, and there is no hardware enforcement of data cache coherency with memory with
respect to other entities in the system which access memory.
It is the responsibility of software to manage this coherency through the appropriate use of the caching inhib-
ited storage attribute, the write-through storage attribute, and/or the data cache management instructions.