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User’s Manual
PPC440x5 CPU Core Preliminary
Page 180 of 589
intrupts.fm.
September 12, 2002
Machine Check Save/Restore Register 1 (MCSRR1)
Set to the contents of the MSR at the time of the interrupt.
Machine State Register (MSR)
All MSR bits set to 0.
Exception Syndrome Register (ESR)
MCI Set to 1 for an Instruction Machine Check exception; otherwise left unchanged.
All other defined ESR bits are set to 0 for an Instruction Machine Check exception; otherwise they are left
unchanged.
Programming Note: If an Instruction Synchronous Machine Check exception is associated
with an instruction, and execution of that instruction is attempted while
MSR[ME] is 0, then no Machine Check interrupt will occur, but
ESR[MCI] will still be set to 1 when the instruction actually executes.
Once set, ESR[MCI] cannot be cleared except by software, using the
mtspr instruction. When processing a Machine Check interrupt
handler, software should query ESR[MCI] to determine the type of
Machine Check exception, and then clear ESR[MCI]. Then, prior to re-
enabling Machine Check interrupts by setting MSR[ME] to 1, software
should query the status of ESR[MCI] again to determine whether any
additional Instruction Machine Check exceptions have occurrred while
MSR[ME] was disabled.
Machine Check Status Register (MCSR)
The MCSR collects status for the Machine Check exceptions that are handled as asynchronous interrupts.
MCSR[MCS] is set by any Instruction Asynchronous Machine Check exception, Data Asynchronous Machine
Check exception, or TLB Asynchronous Machine Check exception. Other bits in the MCSR are set to indicate
the exact type of Machine Check exception.
MCS Set to 1.
IB Set to 1 if Instruction Read PLB Interrupt Request (IRQ) is asserted; otherwise set to
0.
DRB Set to 1 if Data Read PLB Interrupt Request (IRQ) is asserted; otherwise set to 0.
DWB Set to 1 if Data Write PLB Interrupt Request (IRQ) is asserted; otherwise set to 0.
TLBP Set to 1 if the exception is a TLB parity error; otherwise set to 0.
ICP Set to 1 if the exception is an instruction cache parity error; otherwise set to 0.
DCSP Set to 1 if the exception is a data cache parity error that resulted during a DCU
Search operation; otherwise set to 0. See Data Cache Parity Operations on
page 129.
DCFP Set to 1 if the exception is a data cache parity error that resulted during a DCU Flush
operation; otherwise set to 0. See Data Cache Parity Operations on page 129.
IMPE Set to 1 if MCSR[MCS] is set (or would be, if it were not already set) and MSR[ME]
= 0; otherwise set to 0. When set, this bit indicates that a Machine Check exception
happened while Machine Check interrupts were disabled.