Filter
Top Products
User’s Manual
Preliminary PPC440x5 CPU Core
init.fm.
September 12, 2002
Page 87 of 589
DBSR
UDE 0 Unconditional debug event has not occurred
MRR Reset-dependent
Indicates most recent type of reset as follows:
00 No reset has occurred since this field last cleared by software
01 Core reset
10 Chip reset
11 System reset
ICMP 0 Instruction completion debug event has not occurred
BRT 0 Branch taken debug event has not occurred
IRPT 0 Interrupt debug event has not occurred
TRAP 0 Trap debug event has not occurred
IAC1 0 IAC1 debug event has not occurred
IAC2 0 IAC2 debug event has not occurred
IAC3 0 IAC3 debug event has not occurred
IAC4 0 IAC4 debug event has not occurred
DAC1R 0 Data address compare 1 (DAC1) read debug event has not occurred
DAC1W 0 DAC1 write debug event has not occurred
DAC2R 0 DAC2 read debug event has not occurred
DAC2W 0 DAC2 write debug event has not occurred
RET 0 Return debug event has not occurred
ESR MCI 0 Synchronous Instruction Machine Check exception has not occurred
MCSR MCS 0 Asynchronous Instruction Machine Check exception has not occurred
MSR
WE 0 Wait state disabled
CE 0 Asynchronous critical interrupts disabled
EE 0 Asynchronous non-critical interrupts disabled
PR 0 Processor in supervisor mode
FP 0 Floating-point Unavailable interrupts disabledStorage
ME 0 Machine Check interrupts disabled
FE0 0 Floating-point Enabled interrupts disabled
DWE 0 Debug Wait mode disabled
DE 0 Debug interrupts disabled
FE1 0 Floating-point Enabled interrupts disabled
IS 0 Instruction fetch access is to system-level virtual address space
DS 0 Data access is to system level virtual address space
PC 0xFFFFFFFC Initial reset instruction fetched from last word of effective addess space
PVR
OWN System-dependent PVR[OWN] value (after reset and otherwise) is specified by core input signals
PVN System-dependent PVR[PVN] value (after reset and otherwise) is specified by core input signals
Table 3-1. Reset Values of Registers and Other PPC440x5 Facilities
Resource Field Reset Value Comment