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User’s Manual
PPC440x5 CPU Core Preliminary
Page 150 of 589
mmu.fm.
September 12, 2002
program to remove a locked line from the cache. The locking and unlocking of cache lines is generally a
supervisor mode function, as the supervisor has access to the various mechanisms which control the cache
locking mechanism (e.g., the Data Cache Victim Limit (DVLIM) and Instruction Cache Victim Limit (IVLIM)
registers, and the MMUCR). Therefore, the DULXE field provides a means to prevent any dcbf instructions
executed while in user mode from flushing any cache lines.
Note that with the PPC440x5 core, the Cache Locking exception occurs independent of whether the target
line is truly locked or not. This behavior is necessary because the instruction execution pipeline is such that
the exception determination must be made before it is determined whether or not the target line is actually
locked (or whether it is even a hit).
Software at the Data Storage interrupt handler can determine whether the target line is locked, and if so
whether or not the application should be allowed to unlock it.
If DULXE is 0, or if dcbf is executed while in supervisor mode, then the instruction execution is allowed to
proceed and flush the target line, independent of whether it is locked or not.
See Chapter 4, “Instruction and Data Caches” for more information on cache locking.
Instruction Cache Unlock Exception Enable (IULXE) Field
The IULXE field can be used to force a Cache Locking exception type Data Storage interrupt to occur if an
icbi instruction is executed in user mode (MSR[PR]=1). Since icbi can be executed in user mode and since it
causes a cache line to be removed from the instruction cache, it has the potential for allowing an application
program to remove a locked line from the cache. The locking and unlocking of cache lines is generally a
supervisor mode function, as the supervisor has access to the various mechanisms which control the cache
locking mechanism (e.g., the DVLIM and IVLIM registers, and the MMUCR). Therefore, the IULXE field
provides a means to prevent any icbi instructions executed while in user mode from flushing any cache lines.
Note that with the PPC440x5 core, the Cache Locking exception occurs independent of whether the target
line is truly locked or not. This behavior is necessary because the instruction execution pipeline is such that
the exception determination must be made before it is determined whether or not the target line is actually
locked (or whether it is even a hit).
Software at the Data Storage interrupt handler can determine whether the target line is locked, and if so
whether or not the application should be allowed to unlock it.
If IULXE is 0, or if icbi is executed while in supervisor mode, then the instruction execution is allowed to
proceed and flush the target line, independent of whether it is locked or not.
See Chapter 4, “Instruction and Data Caches” for more information on cache locking.
Search Translation Space (STS) Field
The STS field is used by the tlbsx[.] instruction to designate the value against which the TS field of the TLB
entries is to be matched. For instruction fetch and data storage accesses, the TS field of the TLB entries is
compared with the MSR[IS] bit or the MSR[DS] bit, respectively. For tlbsx[.] however, the MMUCR[STS] field
is used, allowing the TLB to be searched for entries with a TS field which is references an address space
other than the one being used by the currently executing process.
See Address Space Identifier Convention on page 138 for more information on the TLB entry TS field.