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MSR (cont.)
Machine State Register
Preliminary PPC440x5 CPU Core User’s Manual
regsumm440core.fm.
September 12, 2002 Page 505 of 589
23 FE1
Floating-point exception mode 1
0 If MSR[FE0] = 0, ignore exceptions mode; if
MSR[FE0] = 1, imprecise recoverable mode
1 If MSR[FE0] = 0, imprecise non-recoverable
mode; if MSR[FE0] = 1, precise mode
24:25 Reserved
26 IS
Instruction Address Space
0 All instruction storage accesses are directed to
address space 0 (TS = 0 in the relevant TLB
entry).
1 All instruction storage accesses are directed to
address space 1 (TS = 1 in the relevant TLB
entry).
27 DS
Data Address Space
0 All data storage accesses are directed to
address space 0 (TS = 0 in the relevant TLB
entry).
1 All data storage accesses are directed to
address space 1 (TS = 1 in the relevant TLB
entry).
28:31 Reserved